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VHDL: When writing testbench for a statemachine, how to monitor internal state

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matrixofdynamism

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I have HDL code for a statemachine type of circuit. I am writing a testbench for it. At the moment I provide it with inputs and than after clk cycle delays use VHDL assert statements on each output of the circuit. This way I have an automatic testbench which shall produce a failure message if any assert statement fails.

However, I think that it would be better if I can actually also read the internal state signal of the circuit in the testbench and use assert statement on that also, this will provide a more complete coverage.

How do I see signals internal to a DUT in a VHDL testbench?
 

There are two options.

1. Put the simulation only asserts inside the DUT itself, inside synthesis translate_ on/off pragmas so they only apply in simulation.

2. Use vhdl 2008 hierarchical signal names. You can access any signal in the simulation at any level using the new <<>> things. Often the easiest way is to alias them.

Alias buried_sig : Std_logic is << signal dut.some_ent.some_sig :std_logic>>;
 

How do I see signals internal to a DUT in a VHDL testbench?
If you're using Modelsim - press on the '+' sign left of the top hirerchy of the "SIM" window and add the required component to the waveform.
 

If you're using Modelsim - press on the '+' sign left of the top hirerchy of the "SIM" window and add the required component to the waveform.

The op asked to perform asserts on the signals in the vhdl, not simply view them in the wave window.
 

hmmm, I have never in my life seen this construct of VHDL. Where did you learn this from?
Where can I find a proper coverage of new futures in VHDL 2008?
 


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