nervecell_23
Member level 1
For instance, to implement an registered 2-bits 5:1 MUX:
1) use 'case' statement:
I wonder whether the following 'array' style implementation would work or not:
1) use 'case' statement:
Code:
reg [1:0] out;
wire [1:0] i_1, i_2, ... , i_5;
always@(posedge clk)
begin
case(sel)
3'b000: out <= i_1;
3'b001: out <= i_2;
...
endcase
endI wonder whether the following 'array' style implementation would work or not:
Code:
wire [1:0] in [0:4];
wire [1:0] i_1, i_2, ... , i_5;
reg [1:0] out;
assign in[0] = i_1;
assign in[1] = i_2;
...
assign in[4] = i_5;
always@(posedge clk)
begin
out <= in[sel];
end