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error- illegal reference to net

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swat123

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i am working in verilog coding. i am getting the following error
" illegal reference to net q "

my code is as follow:-
Code Verilog - [expand]
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----------------------------------------------------------------------------------------------------------------------
  T-flip flop
     
module tff(t,clk,reset,clear,q,qb);
  input t,clk,reset,clear;
  inout q,qb;
  reg q,qb;
 
  
  always@(negedge clk or reset or clear)
  begin
    if(reset==1)
      begin
      q = 0;
      qb = 1;
    end
      
    else if (clear==1)
      begin
        q=0;
        qb=1;
      end    
  else if(t==1 && clk==0)
      begin
      q =!q;
      qb =!qb;
    end
    else
      begin
      q=q;
      qb=qb;
    end
    
    
  end
  
endmodule
  -----------------------------------------------------------------------------------------------------------------------------------
plz help me
 
Last edited by a moderator:

q and qb must be out instead of inout type

I addition, if you intend to write synthesizable code, please refer to the templates for register modelled.

All events must be described edge sensitive. The condition clk = 0 is illegal for a clock.
 

You can't set q as an output port inside always loop as q is declared as of type inout. If you want to use an inout type as an output, then that must be written outside always loop(like assign q=0). If you want to use q as an output port inside always loop, then it must be declared as of type output.
And never declare inout type as reg.
 
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Besides what both FvM and arishsu have mentioned you are using blocking assignments instead of non-blocking assignments in what is supposed to be an edge triggered procedural block (clocked always block, i.e. flip-flop(s)).

Besides that the usage of the reset and clear as asynchronous inputs was discussed on another thread. https://www.edaboard.com/threads/321110/. My advice don't use asynchronous set/preset in the same flip-flop description for an FPGA (an ASIC may have that library element) as none of the latest generation of FPGAs from Altera and Xilinx (perhaps most of the other vendors too) can implement both a reset/preset on the same flop without resorting to an ugly circuit around the flop to emulate the functionality.

Either make both reset/preset synchronous or make the power up state the asynchronous one and the other synchronous.

- - - Updated - - -

Didn't notice at first...your reset and clear do exactly the same thing. Why would you have both?

Also a minor thing but I would use ~ (bitwise inversion) instead of ! (logical not). There is a subtle difference to the way the two behave...
 

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