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Understanding set_input_delay and set_output_delay constraints in TimeQuest for FPGAs

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matrixofdynamism

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The document from altera https://www.altera.com/literature/hb/qts/qts_qii53018.pdf#page=24 gives a mathematics equation for minimum and maximum input and output delays when am FPGA is connected to an external device.

In the figures 7-12 and 7-14, the term cd_altr which clock insertion delay for the FPGA is and cd_ext which is clock insertion delay for external device are being subtracted. WHY?
 

cd_altr and cd_ext is routing delay from oscillator to fpga and external device.
cd_Ext - cd_altr represents clock shift between tco_clk and fpga data capture clock.
 

Why do we need to take this clock shift into account?
Shouldn't maximum input delay on an FPGA input pin be

Input Delay = (cd_ext–cd_altr)+tco_ext+dd

without the cd_altr giving us

Input Delay = cd_ext+tco_ext+dd

??
 

tco_ext is delay measured as skew between external device clock and external device data output - so you cant talk about tco_ext without external clock -> cd_altr.
 

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