Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] right shift operation in verilog

Status
Not open for further replies.

dipin

Full Member level 4
Joined
Jul 16, 2014
Messages
223
Helped
14
Reputation
28
Reaction score
14
Trophy points
18
Activity points
1,731
hi,
i need to do parallel in parallel out right shift operation(in fpga).
in code it is >> . but problem is did anybody know what is the hardware for shift operation . i searched in internet ,one is using 2:1 multiplexer, can i do it using d flipflop, if it possible please give some idea.please give your valuable suggestion..

thanks & regards
 

Without register or flop , you can not perform shift operation.

Give more detail on this , like block diagram ..
 
  • Like
Reactions: dipin

    dipin

    Points: 2
    Helpful Answer Positive Rating
Without register or flop , you can not perform shift operation.

Give more detail on this , like block diagram ..
A shift operation can be well performed in combinational expressions and won't use registers respectively. Clock synchronous sequential shifts using registers are possible, too. The question is about the specification.

A constant shift doesn't even need a multiplexer just wires.
 

I agree .. its depend on specification. but for Shift , dependent signals has to be flopped.
 

Give more detail on this , like block diagram ..

thanks for the replay.
i need to do 1 bit shift to the right for each clock cycle and need to perform this in fpga.did any one know what is the hardware for this in fpga . for each shift i need to add zero to the left side and output the data . for code it is >>,but dont know what is the hardware for the right shift in fpga (inputs are stored in a register and need to perform right shift n times to the same input. after each shift i need to show output)

thanks and regards
 
Last edited:

Verilog:
Code:
always @(posedge clk)
  sdata  <= {1'b0, sdata[MAX_INDX:1]};

VHDL:
Code:
process (clk)
  if rising_edge (clk) then
    sdata <= '0' & sdata(MAX_INDX downto 1);
  end if;

fixed the '1' to the '0', as OP wanted to shift in 0's
 
Last edited:
  • Like
Reactions: dipin

    dipin

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top