[SOLVED] I need support with Synopsys Design Constraints (SDC)

Hi all
I am working on designing a small block for the interface of a DAC. I am new to setting SDC constraints.

First:

For this small block I only need to consider the following constraints in the SDC file and would like the equivalent commands for the SDC file:

1. It should run at a frequency of 20 MHz
2. It should have a fanout load of 1
3. It should have a maximum delay of 500 ps for combination parts (so delay less than 500 ps)

I need help setting these constraints and any other constraints which always should be set, in order to do synthesis. I would really appreciate it if someone could help me with this.

Second:

I am new to SDC files and will likely need to use SDC files more often. I would strongly appreciate it if someone would take some time to either provide me with a start up guide to get me started quickly. The things I am needed to know:

1. the most important basic constraints which need to always be set in every synthesis and how to set them
2. Hints and tips for different scenarios with constraints to be set which I am likely to come across in my design career

Basically, I want to get a good quick start on writing good SDC files for my designs.

Help and support on the above would be greatly appreciated.

Thank you,

You will need create_clock, max_fanout, and max_delay commands for your first question. For your 2nd question I would recommend you get a solvent account and then learn on your own. That is a better approach.

sharath666 said:

You will need create_clock, max_fanout, and max_delay commands for your first question. For your 2nd question I would recommend you get a solvent account and then learn on your own. That is a better approach.

Click to expand...

Thank you, I managed to get the SDC file done yesterday by help from a colleague. what do you mean by a solvent account :thinker: I already have in mind to learn on my own but still if someone has a quick jump start guide summarizing the main constraints to set common to each design (how to set clock frequency, which delays must be set to get good results, constraints which are needed in every design with maybe examples of how to set them) to get me knowing the important things quickly, that would be really beneficial.

https://sso.synopsys.com/idp/Authn/UserPassword

SolvNet is Synopsys' user online support.

I found the solution to my problem thank you anyway :thumbsup:

I just googled and found this which I found to be useful:
http://ebook.pldworld.com/_semiconductors/Actel/Libero_v70_fusion_webhelp/sdc_files.htm

with a bit of reading on the side, one should be able to put together a good SDC file hopefully