Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Synthesis takes too long while doing "Low level synthesis"

Status
Not open for further replies.
S

SharpWeapon

Member level 5
Joined
Mar 18, 2014
Messages
89
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
705
Hello,

A 64-pt FFT works fine, but when I increase it to 4096-pt, synthesis takes too long after reaching "Low level synthesis". Here is the synthesis report. View attachment report.txt

Thanks!
 

What's "too long"? Maybe you should run this over night and see if it completes. Or get a faster computer. From the report it looks like it's going along, doing it's job, and you interrupted it.

Is this Xilinx IP, or your own or somebody elses? You don't give us any information about what you are actually trying to synthesize.
 

I had synthesized the same design in older version, yes it takes a bit long but never this long. I am sure there is some problem, without even getting to implementation, it is taking forever, strange.

Xilinx 6-series.
 

It takes as long as it takes.
If there suddently a spike in synthesis, you probably did something in the source code.
Do you have asynchronours rams? or rams that are being created with logic? that will increase the synth time massively.
 

Hi TrickyDicky. Yeah may be it is the RAMs I have. Here is the report I have for the 64-pt.
Code: 
 128x36-bit dual-port RAM                              : 2
 128x36-bit quad-port RAM                              : 1
 32x36-bit single-port Read Only RAM                   : 1
 64x36-bit single-port Read Only RAM                   : 1
 8x36-bit single-port Read Only RAM                    : 1

Here is also the 4096.

Code: 
 128x36-bit single-port Read Only RAM                  : 2
 2048x36-bit single-port Read Only RAM                 : 2
 32x36-bit single-port Read Only RAM                   : 2
 4096x36-bit single-port Read Only RAM                 : 1
 512x36-bit single-port Read Only RAM                  : 2
 8192x36-bit dual-port RAM                             : 2
 8192x36-bit quad-port RAM                             : 1
 8x36-bit single-port Read Only RAM                    : 2

I am also troubled by the size of the RAM, I checked the manual for maximum RAM size, it is 36 Kb RAM. But in my case (8192x36-bit) is way bigger than the maximum, so I think the synthesizer is using distributed RAM right, so that might be the case for the delay?
 

Are they actually using distributed rams? or linking together many BRAMs?
 

The two dual-port RAMs use BRAM while the quad-port RAM is implemented using distributed RAM. Actually I don't have a quad-port RAM, I only have dual-port RAM, I don't know why the synthesizer choose it.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top