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Signals in a process

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Binome

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Hi,
I'm wondering why I observe such a comportment. I've got a DE0-Nano board and I'm using LEDs to control my design. Here are two different codes:
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ctrl is
	port(
        
		clk		: in  std_logic;
		wdone		: out std_logic := '0');
end ctrl;

architecture rtl of ctrl is
begin
	process(clk)
	begin
		wdone <= '1';
	end process;
end rtl;

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ctrl is
	port(
        
		clk		: in  std_logic;
		wdone		: out std_logic := '0');
end ctrl;

architecture rtl of ctrl is
begin
	process(clk)
	begin
            if rising_edge(clk) then
		wdone <= '1';
            end if;
	end process;
end rtl;
In the first case the LED is flashing green (wdone is equal to '1'), in the second one it doesn't (wdone is '0').
I don't understand why the rising edge of clock seems to be false but the process is running anyway. Please tell me what I don't know.
Thanks.
 

you have to remember that it doesnt run the code on your board, it runs the synthesised version of the code.
In the first one, wdone is stuck at '1'. In the second, it is stuck at '0' until the first rising edge, when it is always '1'. I may have removed this register because it never changes, and then connected the output to the default of '0'.

Check the synthesis warnings for removed logic. and check the RTL diagram.
 

I use Quartus II 13.1 and I don't know how to look at the generated RTL. Can you help me ?

- - - Updated - - -

I've found it.
My signal is the output of a register. Its input is 1'h1. Why doesn't it light the LED?
 

And for the first? what is connected to wdone?
 

Binome said:
I use Quartus II 13.1 and I don't know how to look at the generated RTL. Can you help me ?

- - - Updated - - -

I've found it.
My signal is the output of a register. Its input is 1'h1. Why doesn't it light the LED?
Click to expand...
You should instead learn to run a simulator. Then you will have full access to all that you need to debug the problem.

Kevin
 

Given that the first process doesn't use clk within the process.
Code: 
	process(clk)
	begin
		wdone <= '1';
	end process;
which actually doesn't represent any type of actual hardware, but synthesis most likely sees this as only the line:
Code: 
wdone <= '1';
which will just assign a logic high to the wdone signal/pin

Given that both of the code samples you gave were very simple with only two pins/ports (this is the top level file you are running synthesis and configuring the FPGA with?).

The most likely problem is that you don't have the same sdc file being used to apply the pin location constraints, so either your clock input or your led (wdone) output are not connected correctly in the second case. Are you sure you assigned clk with a pin with an active clock on it (e.g. R8 which has CLOCK_50)?

Regards

- - - Updated - - -

Actually thinking about it more you probably don't have the clock assignment correct. That would explain the difference between the two cases. In the first case clk isn't used so synthesis will ignore the clock and connect the wdone directly to a logic high. In the second case the clock has to exist to load the logic high into the flip-flop, which then shows up at the wdone output.

check that you are using the CLOCK_50 input pin for your clk port.
 

You should instead learn to run a simulator. Then you will have full access to all that you need to debug the problem.
Click to expand...
Basically a good idea, but the first code will unfortunately behave different than synthesized logic in a functional simulation.

Simulator usage should be supplemented by a basic understanding of synthesized VHDL working.

The point is that the clk input is simply ignored in the first code, so wdone is staically wired to '1'.

- - - Updated - - -

I din't hear that the OP complained about wdone not switching in the second case. Thus I understand that clk is undriven intentionally.
 

I don't really understand. The pin assignment is ok. I didn't use a simulator because the code seemed too simple but I'll try...
 

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