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Verilog division in Actel devices

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behrazv

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Does anyone know how Actel implements division? Is this by subtraction or in some other way? I'm having trouble compressing my code resource consumption, and I think it's because I don't know how division works.

Thank you in advance!
 

The question isn't specific to Actel, I think. Usually vendor libraries implement a fast parallel division algorithm, which is combinational by nature, but may be speeded up with additional pipeline registers. Parallel division is very resource consuming and there are effectively no means to reduce the logic usage, except for reducing the data size.

If you don't need single (or a few) clock cycle divison speed, you can refer to a sequential divider which needs e.g. one clock cycle per result bit. Some vendors provide it as ready-to-use IP blocks. If Actel doesn't offer it, write your own or refer to internet resources.
 

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