Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

True Dual Port RAM ALTERA writting and reading problems

Status
Not open for further replies.

DRO

Junior Member level 1
Joined
Feb 25, 2014
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
167
Hi everyone,
I GOT A HUGE PROBLEM
I am trying to store some datas in a ram in order to send them via USB to my computer. I am writting a VHDL code for all of it.
This is how it works :

there is a first block which just sends an adress to the RAM (not considering what is after it, he just sends and sends and sends).Then all what shall be done is just a +1 incrementation of what is at the adress.
I first tried to do it by using the synthax "Type RAM is array () of std_logic_vector() , but it seems like it consumes lot of logic cells of the fpga, not memory blocks (and i am short on logic cells). So i changed for Altsyncram megafunction.
But now there is a problem when i try to write in the RAM. When I increments the content of an adress 5 times for example, i should see the number 5 at that adress (assuming that i have a way to check it on my computer), but that's not the case. I see numbers such as 146 or other big numbers.
I really don't know where is the problem, and i have read altera's document on RAM blocks and all. please can somone help me with this, because it is really bothersome right now. If you want a piece of code no problems just tell me.
thank you.
 

plz post a code

Maybe you're using some reset/set signal on array so its implemented on LC...
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
It sound's like your first attempt didnt infer a ram, and in the second attempt you are accessing the ram incorrectly.
Please post the code.
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
This is the code for the RAM corresponding to my first attempt, using and array of std_logic _vector



Code:
----------------------------------------------------------------------------------

-- Module Name:    RAM - Behavioral 
-- Project Name: 
-- Target Devices: Cyclone
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--    			THIS piece of code is ABOUT THE RAM STORAGE PROCESS..
--   An adress is given by an external modulus, and an incrementation of 1 is done time a specific adress is accessed
--   tHE READING OPERATION IS ONLY DONE WHEN THE COMPUTER ASKS IT, WHEN WE WANT TO CHECK OUT WHAT IS IN THE RAM. The reading 
--   Operation is done from the adress number 0 to the last adress, in one time, and checking successively each adress after another.
--   Every time a process is ended (reading or writting), it sends a flag to the controller, designed in VHDL, telling him that
--   the operation is over. When is time 
---
---
---  									          __________                  ____________
---										  |  adress    |  adress     |____________|
---										  |  sender    |-----------> |____________| datas
---										  |_________|	write      |____________|----------->  to computer
---														     |____________|  read
---														     |____________|
--                                                                                                                      RAM BLOCK
------------------------------------------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-----------------------------------------------------------------------------------------------------------------------------
--     
entity Bram is
	generic (
				
				width_in			:	integer	:= 8;					--Width of data
				addr_bits			:	integer 	:= 11				--Depth of data	(2^10 = 1024 addresses)
			);
	port	(
				clk			:	in std_logic;					      --System clock
				rst			:	in std_logic;					      --System Reset
				addr_out		:	in std_logic_vector (addr_bits - 1 downto 0);   --Output Adress 
				fx_clock : in std_logic;
				addr_in		:	in std_logic_vector (addr_bits - 1 downto 0);   --Input Adresse
				din_valid	:	in std_logic; 							   --Input Adress Validation
				finish  : out std_logic;									   --Finish Signal
				data_out	:	out unsigned (width_in - 1 downto 0);		           --Outut Adress Validation
				dout_valid	:	out std_logic ;							   --Data Out Validation
				aout_valid	:	in std_logic 							   --Adress Out Validaion
			);
end entity Bram;

architecture arc_ram_simple of Bram is
------------------  	Types		------
type ram_arr is array (natural range <> ) of unsigned (width_in - 1 downto 0);

------------------  	Signals		------
signal ram_data		:	ram_arr (0 to 2**addr_bits - 1):=(others =>(others =>'0'));
signal flag_wr			:  std_logic;
signal flag_rd			:  std_logic;
signal addr_ou			:  unsigned (width_in - 1 downto 0):=(others => '0');
------------------  Implementation	------
begin
	
----------------------------------------------------------------------------------------------------------------------
---------	Process din_proc 	-----------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------
-- This is the process which writes the data to the specific  
-- adress sent by an externl modulus at Rising_edge
-- ------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------
	din_proc : process (clk)
	begin
		if rising_edge(clk) then
			if din_valid = '1' then
				if(ram_data (conv_integer(unsigned(addr_in))) = 200) then
				ram_data (conv_integer(unsigned(addr_in))) <=(others =>'0');
				else
				ram_data (conv_integer(unsigned(addr_in))) <= ram_data (conv_integer(unsigned(addr_in))) + 1; 
				flag_wr <= '1';
				end if;
			else
				flag_wr <= '0';
			end if;
		end if;
	end process din_proc;
	
-----------------------------------------------------------------------------------------------------------------------------------
---------	Process dout_proc 	---------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-- The process' output is the required 
-- data from a given address, when the 
-- given address is valid.
----------------------------------------------------------------------------------------------------------------------------------
	dout_proc : process (clk)
	begin
		if rising_edge(clk) then
			if aout_valid = '1' then 						--Output address is valid
				data_out <= ram_data (conv_integer(unsigned(addr_ou)));
				flag_rd <= '1';
			else
				flag_rd <= '0';
			end if;
		end if;
	end process dout_proc;
	
--------------------------------------------------------------------------------------------------------------------------
--- This is the process which sets the adress that shall be read
--- The adresses are read in line, one after another uninterruptedly
-----------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------
  aout_procc : process (clk, addr_ou)
	begin
		if rising_edge(clk) then
			if ((aout_valid = '1') and (addr_ou = 255))then 						
				addr_ou <= (others=>'0');
			else
			  if((aout_valid = '0'))then
				 addr_ou <= (others=>'0');
				else
				addr_ou <= addr_ou + 1;
			end if;
		end if;
	 end if;
	end process aout_procc;
	
--------------------------------------------------------------------------------------------------------------------------
-- Set the signal to the controller, telling him that a writting operation  or a reading is finished
----------------------------------------------------------------------------------------------------------------------------
	finishion : process (clk)
	begin
		if rising_edge(clk) then
			if( flag_rd ='1' or flag_wr='1')then 						
				finish <= '1';
			else
				finish <= '0';
			end if;
		end if;
	end process finishion;
	
	
-----------------------------------------------------------------------------------------------------------------------------
------- Process data_out_valid_proc ------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------
-- Process telling that the datas are good
-- --------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------
	
	data_out_valid_proc : process (clk, rst)
    begin
		if (rst = '1') then 									 --System Reset
			dout_valid      <= '0';
        elsif rising_edge(clk) then
			dout_valid <= aout_valid;
        end if;
    end process data_out_valid_proc;
	
end architecture arc_ram_simple;
 

And here is the piece of code about the RAM, using
the ALTERA RAM MEGAFUNCTION.

Code:
library IEEE;
Library altera_mf;
USE altera_mf.altera_mf_components.all;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_signed.all;
use ieee. math_real.all;


entity distributeur is
	generic(
   ADDRESS_WIDTH 	  : integer := 11;
	Lattency		     : integer := 2;
   DATA_WIDTH 		  : integer := 8;
	DATA_OU_WIDTH 	  : integer := 8
    );


   Port (  Clock					: in std_logic;														-- Horloge de la RAM 100Mhz
			  fx_clock				: In std_logic;														-- Horloge du fx2 48mhz
			  Data_in				: in std_logic_vector (ADDRESS_WIDTH-1 downto 0) :=(others =>'0');
			  fin_lecture_perm	: In std_logic;
			  demande_lecture_perm        : In std_logic;
			  Data_out				: out std_logic_vector (DATA_OU_WIDTH-1 downto 0)); 
			   
end distributeur;


architecture Behavioral of distributeur is
	  type ETAT is (Ecriture,Lecture_perm, ready);					-- Variable des états de la mémoire
	  Signal State : ETAT := Ready;	
	  Signal a: unsigned(7 downto 0) := (others=>'0');
	  Signal b: unsigned(4 downto 0);
	  Signal reset: std_logic := '0';
	  Signal horlogue: std_logic := '0';
	  signal compteur : unsigned (2 downto 0);
	  Signal pass_adress: std_logic := '0';
	  
	  signal rd_en : std_logic :='0';
	  signal wr_en : std_logic :='1';
	  signal wr_adress :  unsigned(ADDRESS_WIDTH - 1 DOWNTO 0);
     Signal write_address :  std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
	  signal read_address :  std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
	  signal adress_lec_perm :  std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
	  signal DATA  : std_logic_vector(DATA_WIDTH - 1 DOWNTO 0) := (others =>'0');
	  signal DAT  : std_logic_vector(DATA_WIDTH - 1 DOWNTO 0) := (others =>'0');
	  signal Sortie  : std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
	  signal val_lue  : std_logic_vector(DATA_WIDTH - 1 DOWNTO 0):=(others =>'0');
	  signal sort :  std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
	  signal rd_adres_interm : std_logic_vector(11 downto 0);
	  signal fin_lecture: std_logic;
	  signal fx_clock_ena: std_logic :='1';
	  signal fin_lecture_clk2: std_logic;
	  
		
--------------------------- HERE IS THE ALTSYNCRAM USED FOR DATA STORAGE------------------------------------------  
------ IT IS A BIDIR DUAL PORT RAM where read and write can be operated at the same time
------ it possesses two adresses one for the port A and another one for the port B
------two different clocks are used for read and write
---------------------------------------------------------------------------------------------------------
COMPONENT altsyncram 
   GENERIC 
     (OPERATION_MODE                    :  STRING  := "BIDIR_DUAL_PORT";
      WIDTH_A                            :  INTEGER := DATA_WIDTH;    -- 1;
      WIDTHAD_A                          :  INTEGER := ADDRESS_WIDTH;    -- 1;
      NUMWORDS_A                         :  INTEGER := 2**ADDRESS_WIDTH;    -- 1;
      OUTDATA_REG_A                      :  STRING  := "CLOCK0";
      ADDRESS_ACLR_A                     :  STRING  := "NONE";
      OUTDATA_ACLR_A                     :  STRING  := "NONE";
      INDATA_ACLR_A                      :  STRING  := "NONE";
      WRCONTROL_ACLR_A                   :  STRING  := "NONE";
      BYTEENA_ACLR_A                     :  STRING  := "NONE";
      WIDTH_BYTEENA_A                    :  INTEGER := DATA_WIDTH;
      WIDTH_B                            :  INTEGER := DATA_WIDTH;    -- 1;
      WIDTHAD_B                          :  INTEGER := ADDRESS_WIDTH;    -- 1;
      NUMWORDS_B                         :  INTEGER := 2**ADDRESS_WIDTH;    -- 1;
      RDCONTROL_REG_B                    :  STRING  := "CLOCK1";
      ADDRESS_REG_B                      :  STRING  := "CLOCK1";
      INDATA_REG_B                       :  STRING  := "CLOCK1";
      WRCONTROL_WRADDRESS_REG_B          :  STRING  := "CLOCK1";
      BYTEENA_REG_B                      :  STRING  := "CLOCK1";
      OUTDATA_REG_B                      :  STRING  := "UNREGISTERED";
      OUTDATA_ACLR_B                     :  STRING  := "NONE";
      RDCONTROL_ACLR_B                   :  STRING  := "NONE";
      INDATA_ACLR_B                      :  STRING  := "NONE";
      WRCONTROL_ACLR_B                   :  STRING  := "NONE";
      ADDRESS_ACLR_B                     :  STRING  := "NONE";
      BYTEENA_ACLR_B                     :  STRING  := "NONE";
      WIDTH_BYTEENA_B                    :  INTEGER := DATA_WIDTH;
      BYTE_SIZE                          :  INTEGER := DATA_WIDTH;
      READ_DURING_WRITE_MODE_MIXED_PORTS :  STRING  := "DONT_CARE";    
      RAM_BLOCK_TYPE                     :  STRING  := "M4K";    
      INIT_FILE                          :  STRING  := "UNUSED";    
      INIT_FILE_LAYOUT                   :  STRING  := "PORT_A";    
      MAXIMUM_DEPTH                      :  INTEGER := 2048;    
      INTENDED_DEVICE_FAMILY             :  STRING  := "Cyclone";
      LPM_HINT                           :  STRING  := "BOGUS");

   PORT (  wren_a  : IN STD_LOGIC := '0';   
           rden_b, clock0, clock1, clocken1 : IN STD_LOGIC := '1';   
			  data_a			           : IN STD_LOGIC_VECTOR(WIDTH_A - 1 DOWNTO 0):= (OTHERS => '0');
           address_a               : IN STD_LOGIC_VECTOR(WIDTHAD_A - 1 DOWNTO 0) := (OTHERS => '0');
           address_b               : IN STD_LOGIC_VECTOR(WIDTHAD_B - 1 DOWNTO 0) := (OTHERS => '0');
           q_a                     : OUT STD_LOGIC_VECTOR(WIDTH_A - 1 DOWNTO 0);
           q_b                     : OUT STD_LOGIC_VECTOR(WIDTH_B - 1 DOWNTO 0));

END COMPONENT; 
	
begin
	
ram: altsyncram  port map
		  (
			clock0 => clock,
			clock1 => fx_clock,
			data_a => data,
			clocken1 => fx_clock_ena,
			address_a =>  write_address,
			address_b  => read_address,
			wren_a => wr_en,
			rden_b => rd_en,
			q_a => sortie,
			q_b => sort
			);

----------------------- THE RAM STATE MACHINE -----------------------------------------------
--------------  It uses the slowest of both clocks, the fx_clock
--------------  Starts with writting and when reading is asked (demand_lecture_perm ='1') then it performs reading, but reading
--------------  only, and stops writting.In the end (fin_lecture_perm = '1'),we go back to the state READY,the writting
-------------- the state "Ready" is used for lattency, and worth a clock top.
-------------------------------------------------------------------------------------------------------------------------

	
Histogram_state_machine: process(fx_Clock)
		begin
			
			if(falling_edge(fx_Clock)) then
			
			--Etat 1 de la mémoire: Si elle est occupée 
			--------------------------------------------
				Case State is			
			--Etat 2 de la mémoire: lorsqu'elle est libre
			---------------------------------------------
				when ready =>
							  State <= Ecriture;

			--Etat 2 de la mémoire: En lecture
			---------------------------------------------
				when Ecriture =>
						if( demande_lecture_perm = '1') then
							State <= lecture_perm ;
						else
							State <= Ecriture;
						end if;
	
					
				when lecture_perm =>
						if(fin_lecture_perm = '1') then
								State <= Ready;
						else
							   State <= lecture_perm ;
						end if;
						
				end case;
			end if;
			
		end process;
		
-------------------------------READING PROCESS OF THE RAM --------------------------------------------
---------------- La RAM est lue de la première adresse à la dernière, successivement et sans intérruption
---------------- Cette incrémentation de l'adresse de lecture n'est faite que lorsque l'on est à l'état de 
---------------- "lecture permanente".  	On revient à zero lorsque la dernière case de la mémoire est atteinte
-------------------------------------------------------------------------------------------------------------	
	
process(fx_clock, read_address, compteur)
	
	begin
		if(rising_edge(fx_clock)) then
			if ( state = Lecture_perm ) then 
				
				if( read_address = 2047 ) then
					read_address <=(others =>'0');
				else
					read_address <= read_address + 1;
				end if;
			else
				read_address <=(others =>'0');
			end if;
		end if;
  end process;

  
data_out <= sort;								----- Donnée en sortie de la mémoire vers le module de communication

write_address <= Data_in;					----- L'adresse d'écriture corresponds au port "Data_in" à tout instant

Data <= sortie + 1 ;							----- Les données écrite à une adresse précise (write adress) sont: le résultat renvoyé deouis l'adresse en question, incrémenté de 1

with state select
		wr_en <=       '1' when Ecriture,		----- Permission d'écrire uniquement losque l'on est en mode écriture
					      '0' when others;

  --Data_in(ADDRESS_WIDTH-1 downto 3);
		
end Behavioral;
 

Code:
if rising_edge(clk) then
  ...	
  if(ram_data (conv_integer(unsigned(addr_in))) = 200) then
    ram_data (conv_integer(unsigned(addr_in))) <=(others =>'0');
  else
    ram_data (conv_integer(unsigned(addr_in))) <= ram_data (conv_integer(unsigned(addr_in))) +1; 
    flag_wr <= '1'; 
  end if;
			....

looks like you want to read and write in the same cycle, thats why its impelmented on lut ont on bram
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
The first code did not infer a ram because you are trying to do a read and a write in the same clock cycle. This is impossible. You need to read in the first clock and then write back in the 2nd clock. If you need instant updates, you may need to clock the ram at 2x frequency.

As for the 2nd code - you probably have problems because you are reading at the fx_clock rate, and writing at the clock rate. Again, see above problem.

And finally, have you simulated both of these? I think the problem would be pretty obvious with the 2nd code.

While Im looking at code - can I encourage you to stop using non-standard VHDL libraries, ie. std_logic_arith and std_logic(un)signed. They are not part of the VHDL standard. You should use numeric_std instead.
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
Okaaaaaay!..thank you very much!!!!!
I will try these.
Well, about what you said, TrickyDicky, it seems like there are some kind of operations
that i can't do whithout those libraries, like conv_unsigned (and its brothers). Do you
think that NUMERIC_STD has equivalent functions that can help it?
And about the simulation, the thing is that i am more proficient with ISE isim, so i usually do it there.
But since ISIM can't simulate ALTERA MEGAFUNCTION, i try to do it on MODELSIM
but i have some difficulties visualizing the RAM content, so wander if i can perfectly do it in Signal Tap.
Right now i am trying.
(Yes it is my first time with ALTERA).
 

Why can't you look at the RAM contents in modelsim? You should be able to look at the contents even if the memory array is in a variable (unlike Vivado's XSIM).

If you use Signal Tap you'll get what synthesis thinks you design is supposed to represent and won't necessarily be verifying the functionality of your source HDL.

- - - Updated - - -

I've found it useful to make small testbenches for IP to see how it behaves if I haven't used it before. So why don't you make a testbench for the RAM and perform some writes and reads to it, so you understand how to properly control it.
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
the ram contents are buried inside the megafunction, you may have to search for them.

for the equivolent in numeric std:
ram_data (to_integer(unsigned(addr_in))) <= ram_data (to_integer(unsigned(addr_in))) +1;

numeric_std has equivolent functions that std_logic_arith (usually with much better names) and has and many many more.
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
Hello, me again.
Okay i am trying to simulate again in MODELSIM, but it really seems like
i have some troubles. Unlike on ISE SIM, it is really complicated to verify internal signals.
When i try to look at the "I1" unit under test, i see a lot of "variables" which seem to
correspond to particuliar wires of some logic cells. That really get me lost.
Once again i am not used to Modelsim so try to do like on ISIM (of XILINX).
I made a testbench
- Set the EDA after Compilation
- I can see the behaviours of all the ports of my top level (UUT)
but i can't watch internal signal properly. More precisely I can't tell
where they are in the "Instance" window of Modelsim.
 

You might be compiling with optimizations enabled, which can limit access to internal signals. Look up optimization and or visibility in the modelsim user guide.
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
when you invoke vsim, use the -novopt option:

vsim -novopt my_ent

That gets you visibility on all internal signals and variables.

IIRC, the memory contents in the altsyncram are stored in a shared variable about 3 entities down.
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
Okay, thank you everybody ads-ee, TrickyDicky and axcdd, i succedded in viewing my RAM in the simulation. I went to "View -> Memory List" and viewed every
and ech cases of my memories ( but still i can't watch all the memory content at once because it is a more than 2 dimensions Mem slice, and i don't know why,
so i watched each adress alone.)
And i finlly figured out the problem. When for example i write a number at the adress n°0 first ("150" for example), the same number
is written to the next adress i select ( if it is the adress number 12, it will contain the number 151, since i make a "+1" in my vhdl program).
So it doesn't even read what is in the adress before writting. It holds the value stored in the previous adress selected.
I think, like you said TrickyDicky, I don't write and read at the corredct cycles. I will try to make a more elaborate state machine or use
adressstalls to correct it.
PS/ I AM STILL WORKING ON THE ALTSYNCRM
 

Okay, I have elaborated the state Machine and It seems to work well, apart from one point :roll: (sorry to bother again).
there is a state which is not entered, and when it comes to that state, it seems like the state machine doesn't go on anymore.

---> [ ready ] ---->[lattence_1]------>[Lecture]------>[Ecriture] (or) [lattence_2]
| |
| |
[Ready] [Ecriture]

The stte i am talking bout is the [lattence_2] state.

here is the piece of code which does that.
Code:
    PORT (  wren_a 					  : IN STD_LOGIC := '0';   
           clock0			 			  : IN STD_LOGIC := '1';   
			  data_a			           : IN STD_LOGIC_VECTOR(WIDTH_A - 1 DOWNTO 0):= (OTHERS => '0');
           address_a               : IN STD_LOGIC_VECTOR(WIDTHAD_A - 1 DOWNTO 0) := (OTHERS => '0');
           q_a                       : OUT STD_LOGIC_VECTOR(WIDTH_A - 1 DOWNTO 0));

END COMPONENT; 
	
begin
	
ram: altsyncram  port map
		  (
			clock0 => clock,
			data_a => Data,
			address_a => write_address,
			wren_a => wr_en,
			q_a => Sortie
			);

----------------------- MACHINE D'ETAT DE LA RAM -----------------------------------------------
--------------  Elle change sous front montant de fx_clock 
--------------  Au début elle commence en écriture
--------------  Ensuite, lorsqu'il y a demande d'une lecture (demande_lecture_perm ='1'), elle se met en mode lecture
--------------  seule et arrete d'écrite.   Lorsque c'est fini (fin_lecture_perm = '1'), on repasse à l'etat ready, puis lecture
--------------  L'etat "Ready" sert ici d'étape créant une lattance équivalent à un coup d'horloge
-------------------------------------------------------------------------------------------------------------------------


		
------------------------------- Processus de Lecture de La RAM --------------------------------------------
---------------- La RAM est lue de la première adresse à la dernière, successivement et sans intérruption
---------------- Cette incrémentation de l'adresse de lecture n'est faite que lorsque l'on est à l'état de 
---------------- "lecture permanente".  	On revient à zero lorsque la dernière case de la mémoire est atteinte
-------------------------------------------------------------------------------------------------------------	

State_machine: process (clock) 
	begin
		if(rising_edge(clock)) then
			case state is
				when  Ready =>
					if(signal_ent ='1') then
						state <= lattence_1;
					else 
		            state <= Ready;
					end if;
				
				when  lattence_1 =>
						state <= Lecture;
						
				when  Lecture =>
					if(demande_lecture_perm ='1') then
						 state <= Lattence_2;
					else
						 state <= Ecriture;
					end if;
				 
				when Ecriture =>
						state <= Ready;
				when  lattence_2 =>
						state <= Ecriture;
			end case;
		end if;
	end process;

DATA <= sortie + 1 when state = Ecriture else
				(others =>'0');
wr_en <= '1' when state= Ecriture else '0';

WR_ENA <= wr_en;	

Data_out <= sortie;

		
end Behavioral;

I think this will be the last problem to encounter on this. So if you please have a suggestion.
 

Have you got a testbench for this design?
 
  • Like
Reactions: DRO

    DRO

    Points: 2
    Helpful Answer Positive Rating
Oops! my bad sorry, the error was in fact in the test bench :lol: !!..
Okay!
REALLY, THANK YOU EVERYBODY!
i am going to make a summ up of all these, then post it for everyone who has the
same problem!.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top