niala72
Newbie level 6
Hello,
I am using QUARTUS II 13.1 Web Edition.
Yesterday I have found another bug, when a signal is named pixels_y2 it generates a strange error and if I rename it to pixels_z2 there is no error. Other signals pixels_x0, 1, 2, 3 and so on give no error, idem pixels_y0 and 1. Very very strange.
Now I have tried for many hours to suppress this error :
cannot be used when clkselect port is not used or is a constant
The chip is a CYCLONE III or CYCLONE IV. The clock mux has 4 clock inputs. And also the tool does not accept if I connect the two PLL outputs with the clock inputs 2 and 3. It claims only one PLL input, contrary of the spec !!!
And I have tried many different ways to drive the select inputs 0 and 1 but the tool refuses to use more than one clock input, then WHY a multiplexor if i cannot use at least two pins ???
WHAT IS MY MISTAKE ???
I HAVE FOUND !!!
Firstly when I converted two pins freq0 and freq1 to a bus I named it freq1[1..0] but the 1 before [ was not in the individual signals freq[1] and freq[0] so the bus entries were bad, no signal at the select inputs of the clock bus. Error message not very easy to understand !
Secondly this CLOCK MUX has several limitations not very explained in the Cyclone IV family datasheet.
The clock inputs 2 and 3 are reserved for a PLL not two !!! We can take two outputs of the same pll (2 pll max in the EP4CE6 and CE10).
AND ALSO there is a problem with the FITTER. It is necessary to connect the pin CLK0 to the clock 0 input of the mux, not the 1 input !!!
Now it succeeds in a CE6 or CE10.
I am using QUARTUS II 13.1 Web Edition.
Yesterday I have found another bug, when a signal is named pixels_y2 it generates a strange error and if I rename it to pixels_z2 there is no error. Other signals pixels_x0, 1, 2, 3 and so on give no error, idem pixels_y0 and 1. Very very strange.
Now I have tried for many hours to suppress this error :
cannot be used when clkselect port is not used or is a constant
The chip is a CYCLONE III or CYCLONE IV. The clock mux has 4 clock inputs. And also the tool does not accept if I connect the two PLL outputs with the clock inputs 2 and 3. It claims only one PLL input, contrary of the spec !!!
And I have tried many different ways to drive the select inputs 0 and 1 but the tool refuses to use more than one clock input, then WHY a multiplexor if i cannot use at least two pins ???
WHAT IS MY MISTAKE ???
I HAVE FOUND !!!
Firstly when I converted two pins freq0 and freq1 to a bus I named it freq1[1..0] but the 1 before [ was not in the individual signals freq[1] and freq[0] so the bus entries were bad, no signal at the select inputs of the clock bus. Error message not very easy to understand !
Secondly this CLOCK MUX has several limitations not very explained in the Cyclone IV family datasheet.
The clock inputs 2 and 3 are reserved for a PLL not two !!! We can take two outputs of the same pll (2 pll max in the EP4CE6 and CE10).
AND ALSO there is a problem with the FITTER. It is necessary to connect the pin CLK0 to the clock 0 input of the mux, not the 1 input !!!
Now it succeeds in a CE6 or CE10.
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