post synthesis functional and timing simulation results?

Confused about the post synthesis functional and timing simulation results by Synopsys Design Compiler. I tried to simulate and synthesize a decoder. The code is very simple.

module decode (in, out);
input [3:0] in;
output [15:0] out;
assign out = 1'b1 << in;
endmodult
part of fixture code:
`timescale 1ns/10ps
............
$monitor($time," in=%b(%d), out=%b", in, in, out);
............
in = 4'b0000;
#100 in = 4'b0001;
#100 in = 4'b0010;
#100 in = 4'b0011;
#100 in = 4'b0100;
#100 in = 4'b0101;
#100 in = 4'b0110;
post synthesis functional and timing simulation results by DC COmpiler:

0 in=0000( 0), out=xxxxxxxxxxxxxxxx
1 in=0000( 0), out=0xxxxx0xx0xxxxxx
1 in=0000( 0), out=0000000x000x0xxx
1 in=0000( 0), out=000000000000000x
1 in=0000( 0), out=0000000000000001
100 in=0001( 1), out=0000000000000001
101 in=0001( 1), out=0000000000000011
101 in=0001( 1), out=0000000000000010
200 in=0010( 2), out=0000000000000010
201 in=0010( 2), out=0000000000000000
201 in=0010( 2), out=0000000000000100
300 in=0011( 3), out=0000000000000100
301 in=0011( 3), out=0000000000001100
301 in=0011( 3), out=0000000000001000
400 in=0100( 4), out=0000000000001000
401 in=0100( 4), out=0000000000000000
401 in=0100( 4), out=0000000000010000
500 in=0101( 5), out=0000000000010000
501 in=0101( 5), out=0000000000110000
501 in=0101( 5), out=0000000000100000
600 in=0110( 6), out=0000000000100000
601 in=0110( 6), out=0000000000000000
601 in=0110( 6), out=0000000001000000

You can see the output is not corresponding to the input. There are some delay fro the output. And some place have some error. Do you think this synthesis is successful or is not? Is the output delay corresponding to input is permittable in the design?

Is the output delay corresponding to input is permittable in the design?

Click to expand...

I guess its not , unless your design is sequential..

You can achieve the same results by using a combinational 16:1 Mux with 16 bit inputs and 4 bit select. But ur code needs to be changed.

Please post ur NETLIST for omre comments..


rgds

My netlist is as following: what's wrong with that?
how to get a combinational 16:1 Mux with 16 bit inputs and 4 bit select after synthesis? how to wirte the code?

module decode ( in, out );
input [3:0] in;
output [15:0] out;
wire n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
n157;
N2P U37 ( .X(n146), .A1(in[1]), .A2(in[2]) );
N2P U38 ( .X(n147), .A1(in[1]), .A2(n156) );
N2P U39 ( .X(n148), .A1(in[2]), .A2(n157) );
N2P U40 ( .X(n149), .A1(n156), .A2(n157) );
N2P U41 ( .X(n150), .A1(in[3]), .A2(in[0]) );
N2P U42 ( .X(n151), .A1(in[3]), .A2(n154) );
N2P U43 ( .X(n152), .A1(in[0]), .A2(n155) );
N2P U44 ( .X(n153), .A1(n154), .A2(n155) );
N2P U45 ( .X(out[15]), .A1(n146), .A2(n150) );
N2P U46 ( .X(out[14]), .A1(n146), .A2(n151) );
N2P U47 ( .X(out[13]), .A1(n148), .A2(n150) );
N2P U48 ( .X(out[12]), .A1(n148), .A2(n151) );
N2P U49 ( .X(out[11]), .A1(n147), .A2(n150) );
N2P U50 ( .X(out[10]), .A1(n147), .A2(n151) );
N2P U51 ( .X(out[9]), .A1(n149), .A2(n150) );
N2P U52 ( .X(out[8]), .A1(n151), .A2(n149) );
N2P U53 ( .X(out[7]), .A1(n146), .A2(n152) );
N2P U54 ( .X(out[6]), .A1(n153), .A2(n146) );
N2P U55 ( .X(out[5]), .A1(n148), .A2(n152) );
N2P U56 ( .X(out[4]), .A1(n148), .A2(n153) );
N2P U57 ( .X(out[3]), .A1(n147), .A2(n152) );
N2P U58 ( .X(out[2]), .A1(n147), .A2(n153) );
N2P U59 ( .X(out[1]), .A1(n152), .A2(n149) );
N2P U60 ( .X(out[0]), .A1(n153), .A2(n149) );
V1N U61 ( .X(n154), .A(in[0]) );
V1N U62 ( .X(n155), .A(in[3]) );
V1N U63 ( .X(n156), .A(in[2]) );
V1N U64 ( .X(n157), .A(in[1]) );
endmodule

whizkid said:

Is the output delay corresponding to input is permittable in the design?

Click to expand...

I guess its not , unless your design is sequential..

You can achieve the same results by using a combinational 16:1 Mux with 16 bit inputs and 4 bit select. But ur code needs to be changed.

Please post ur NETLIST for omre comments..


rgds
WHIZKID

Click to expand...

Could you tell what N2P and V1N cells are....
Please post description from Std cell data sheet.

Mux can be implemented by a simple case statement..
Check verilog book by palnitkar.

I think V1N is inverter and N2P is 2-input AND gate. what can we get from the cell description?
`timescale 1 ps / 1 ps

`celldefine
module V1N ( X , A );
input A ;
output X ;

not # (43:127:215,54:159:270) M (X ,A );
specify
specparam
CDR2$X = 400,
KCL_RISE$X = 61,
KCL_FALL$X = 41,
KCL2_RISE$X = 61,
KCL2_FALL$X = 54,
ODF$X = 1800,
ILF$A = 100;
(A -=> X)=(43:127:215,54:159:270);
endspecify`timescale 1 ps / 1 ps

`celldefine

module N2P ( X , A1 , A2 );
input A1 , A2 ;
output X ;

and # (158:459:780,134:391:664) A (X ,A1 ,A2 );
specify
specparam
CDR2$X = 700,
KCL_RISE$X = 31,
KCL_FALL$X = 18,
KCL2_RISE$X = 31,
KCL2_FALL$X = 27,
ODF$X = 3600,
ILF$A1 = 100,
ILF$A2 = 100;
(A1 +=> X)=(158:459:780,134:391:664);
(A2 +=> X)=(158:459:780,134:391:664);
endspecify
endmodule
`endcelldefine

endmodule
`endcelldefine

whizkid said:

Could you tell what N2P and V1N cells are....
Please post description from Std cell data sheet.

Mux can be implemented by a simple case statement..
Check verilog book by palnitkar.

Click to expand...

DO you do STA? What is your design & timing constraint?