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Driving a module twice its operating CLK

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SharpWeapon

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Hi People,

I was wondering how a module would handle when feed with inputs, at twice the Freq of the operating clock Freq of the module. Let me try to make it clear, say I have a serial data input with clock frequency, CLK, to my Arithmetic_module. My Arithmetic_module operates at CLK/2, which means it gives its output every CLK/2. So, how would the Arithmetic_module do to all the fast data streaming if it doesn't have a buffer. Will it ignore the inputs coming every CLK and take only inputs at every CLK/2?

Thanks!
 

Your description isn't partcularly clear, but the module might read input data at both clock edges.

Besides reading the input, the module must be able to process the input data rate continuously. This shouldn't be a problem if deserialization takes place.
 

Thank you for your reply. I don't know which part is not clear for you.
Arch.jpg
Please see the picture attached. The input is streaming at CLK and the Arth-Element is clocked at half CLK. Assume the input stream is a block of 16 points. So, for the first 8 clocks the Arth-Element s not operating, after 8 clocks, it will start operating on {(0,8)(1,9)...(7,15)}, what will happen to the data (8 to 15) from the delay output(Or A in the picture)?

Thanks, It must be clear now. :)
 

I think, the discussion is pointless without an exact specification of input data and intended arithmetic operation. I keep my statement, dual edge processing might be able to do what you ask. It will split the data in two pathes, if it can be easily joined to the single rate data stream depends on the operation.

The other question is if it would be easier to operate the arithmetic at doubled clock frequency.
 

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