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problem with my code: frequency divider

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bob2987

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Hi all!

I would like to create a ferquency_divider i write this code but it doesn't work, if anyone find a error.

Thank you.

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Code VHDL - [expand]
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library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
 
entity diviseur is
    Port ( reset : in STD_LOGIC;
           clk : in STD_LOGIC;
           s : out STD_LOGIC);
end diviseur;
 
architecture Behavioral of diviseur is
signal s1:  std_logic;
signal CPT: std_logic_vector (2 downto 0); 
begin
process(clk,reset)
begin
if reset = '0' then CPT<="000";
    elsif (clk'event and clk='1') then
        if CPT="110" then 
        CPT<="000";
        s1 <= not s1;
        s <= s1;
        else CPT<=CPT+1;
        end if;
end if;
end process;
end Behavioral;


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Last edited by a moderator:

Re: problem with my code

Initialize the signals s and s1 on reset.
Code: 
if reset = '0' then CPT<="000";
s1<='0';
s<='0';
 

Mmmh, I was going over that code to test my vhdl reading skills (verilog user here), but I couldn't really find anything. As in, I would expect it to work if you used that on real hardware. All registers initialized to 0 by default and off you go.

On simulation I would expect it to show big red X's, due to a bunch of uninitialized registers ... as pointed out by kommu4946. Hint to the OP: if you simulated it, next time post a screenshot of that simulation. Makes it a lot easier. :)

About the only thing I think I would change is to move that "s <= s1;" outside of that "if CPT="110" then" clause. That way it shows that you are clocking that output signal on every positive edge of the clock signal, not just when the counter rolls over. Which one is considered better vhdl style?
 

mrflibble said:
About the only thing I think I would change is to move that "s <= s1;" outside of that "if CPT="110" then" clause. That way it shows that you are clocking that output signal on every positive edge of the clock signal, not just when the counter rolls over. Which one is considered better vhdl style?
Click to expand...

I would move the "s <= s1;" outside the process, to make it unclocked. The extra register (and delay) when having it inside the process is probably not wanted. The reason for "s1" is that "s" can't be inverted directly, since outputs can't be read.

I also suggest that the OP starts using numeric_std instead of the old non-standard libraries, and changes the type for CPT to "unsigned(2 downto 0)".
 

You didn't initialize 's' and 's1'...
 

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