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[SOLVED] GENERIC MAP in VHDL in STructural modelling

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graphene

graphene

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Hallo,

I want to design a N-bit counter as a top module with 2 sub modules as a 2 bit counter and a N-2 bit counter. The point here is about generic mapping.

I want the top module to be used to define the bit-size of the counter and thus the module should work.

I am including my code in this order
PART A: Top,
PART B: N-2 counter and
PART C: 2 bit counter.

The point is totally about defining or mapping the bit-length from the top module to the component underneath. Can someone suggest me with tips. Lets say I want to use it as a 64 bit or 128 bit counter as I wish.

PART A... TOP MODULE
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- top module entity declaration
entity counter_N_bit is

	generic(
	MAX_WIDTH : natural := 128
	);
	
    Port ( IN_CLK : in  STD_LOGIC;
           IN_EN : in  STD_LOGIC;
		   -- carry output from 2 bit counter
		   OUT_CARRY : out  STD_LOGIC;
		   -- test outputs of individual module
		   OUT_COUNT_2_BIT : out  STD_LOGIC_VECTOR (1 downto 0);
		   OUT_COUNT_Nminus_2BIT : out  STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0);
           -- final counter output
		   OUT_COUNT_TOP : out  STD_LOGIC_VECTOR (MAX_WIDTH-1 downto 0)
	);
		   
end counter_N_bit;

architecture Behavioral of counter_N_bit is
	
-- list of signals declarations
	signal slv_temp_2_bit : STD_LOGIC_VECTOR (1 downto 0); -- 2-bit output signal from fast counter 
	signal slv_temp_126_bit: STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0); -- N-2-bit output signal from slow counter 
-- 	signal sl_enable_slow: STD_LOGIC; -- the signal that enables the second counter
	
-- calling the 2 bit fast counting module
	component counter_fast_2 
	
		Port ( IN_CLK : in  STD_LOGIC;
			   IN_EN : in  STD_LOGIC;
			   OUT_CARRY : out  STD_LOGIC;
			   OUT_COUNT_2BIT : out  STD_LOGIC_VECTOR (1 downto 0)
		);
	end component;
	
	
-- calling the 126 bit slow counting module
	component counter_slow_N_minus_2bit
		Generic(
			MAX_WIDTH : natural := 128 -- no of bits for the present testing
		);
		Port ( IN_CLK : in  STD_LOGIC;
			   IN_EN : in  STD_LOGIC;
			   OUT_COUNT_Nminus_2BIT : out  STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0)
		);
	end component;
	
	
-- begin of the top module process
	begin
		counter_fast: counter_fast_2 port map ( IN_CLK => IN_CLK,
												IN_EN => IN_EN,
												OUT_CARRY => OUT_CARRY,
												OUT_COUNT_2BIT => slv_temp_2_bit -- 2-bit output is signal
										);

	
		counter_slow: counter_slow_N_minus_2bit generic map (MAX_WIDTH => MAX_WIDTH) 
									 port map ( IN_CLK => IN_CLK,
									    		IN_EN => sl_enable_slow, -- enable signal after bitwise AND operation of value from the previous counter
												OUT_COUNT_Nminus_2BIT => slv_temp_126_bit -- MSB for the final counter value
										);
		

-- check for the outputs directly from the two counters	
	OUT_COUNT_2_BIT <= slv_temp_2_bit;
	OUT_COUNT_Nminus_2BIT <= slv_temp_126_bit; 

-- concatenating the MSB and LSB from left to right
	OUT_COUNT_TOP <= slv_temp_126_bit & slv_temp_2_bit; 
		
end Behavioral;


PART B

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;


entity counter_slow_N_minus_2bit is

	Generic(
		MAX_WIDTH : natural := 128 -- no of bits for the present testing
	);
    Port ( IN_CLK : in  STD_LOGIC;
           IN_EN : in  STD_LOGIC;
           OUT_COUNT_Nminus_2BIT : out  STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0) -- 126 bit (total Width-2) output for the MSB of the final counter value
	);
		   
end counter_slow_N_minus_2bit;

architecture Behavioral of counter_slow_N_minus_2bit is
	
	signal slv_count_slow : STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0) := (others => '0');
	
begin
	
	sync_process: process (IN_CLK)
		
		begin
			if (rising_edge(IN_CLK)) then
				if (IN_EN='0') then
					slv_count_slow <= slv_count_slow;
				elsif (IN_EN='1') then
					slv_count_slow <= slv_count_slow +1;
				end if;
			end if;
	
		end process;
	
	OUT_COUNT_Nminus_2BIT <= slv_count_slow;
	
end Behavioral;

PART C
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity counter_fast_2 is

    Port ( IN_CLK 			: in  STD_LOGIC;
           IN_EN 			: in  STD_LOGIC;
		   OUT_CARRY 		: out  STD_LOGIC; -- 2 bit output for the LSB of the counter value
           OUT_COUNT_2BIT 	: out  STD_LOGIC_VECTOR (1 downto 0) -- 2 bit output for the LSB of the counter value
	);
		   
end counter_fast_2;

architecture Behavioral of counter_fast_2 is
	
	signal slv_count_2bit : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
	
begin
	
	sync_process: process (IN_CLK)
		
		begin
			if (rising_edge(IN_CLK)) then
				if (IN_EN='1') then
					slv_count_2bit <= slv_count_2bit +1;
				elsif (IN_EN='0') then
					slv_count_2bit <= slv_count_2bit;
				end if;
			end if;
	
		end process;
	
	OUT_CARRY <= slv_count_2bit (0) AND slv_count_2bit (1); -- carry value that enables the next counter
	OUT_COUNT_2BIT  <= slv_count_2bit; -- 2 bit counter value
	
end Behavioral;
 

I dont really understand what you are asking. Have you tried simulating? does it work?
I will comment though - calling a signal slv_temp_126_bit when it could be any size is misleading.

[pedant]
Also, std_logic_unsigned is a non-standard VHDL library. std_logic_vectors werent not meant to be treated as numbers. You should use numeric_std library instead.
[/pedant]
 

hi Tricky,

sorry fr the pits in the code... i simulated and it works well (both the sub modules and also the top module).. but only when I define the size as a fixed value in the generics.
.
Now, I want to define the size of my counter from the top module either as a 126 bit or 64 bit or a 32 bit or so.....
.
for that

1) I dont know who to use generic option in two of my modules

a) top module
b) my N-2 counter module.
 

well counter_fast_2 has no generic option.

And to map a value, you just use generic map, like you did in your code already:

Code: 
my_inst : counter_N_bit
generic map (
  MAX_WIDTH => 10  --or whatever you want it to be
)

--etc
 
I want to do the same for the (N-2) module .. perhaps 126 or 62 or 30 bits for the second module.. how do I do that?
 

but what is it you want to assign the generic to?
 
sorry for my english and sincere thanks for your support.

let me ttry to define my issue now.

I need a generic value to be defined in the top module. This value should be carried to the components I am using in ym sub module.

Ex: 128 bit counter is divided into a 2 bit counter and a 126 bit counter.
or 64 bit counter is divided into a 2 bit counter and a 62 bit counter.

This particular value of bit length (128 or 64 ) I wish to define in my top module.

So that when I use WIDTH-2 as a value in my sub modules it should refer to the top module for the bit size and work accordingly.
 

There are many examples and tutorials out there how to use generics. And the code you posted already contains a generic MAP.
So short of re-writing your code for you, I dont know what you want?
 

I read several tutorials online.. problem is to carry the geenric value defined in the top module to the sub modules.
 

Like the others I don't know what you are having a problem with as you already have a generic at the top level that you've used in a lower level module.

Code VHDL - [expand]
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-- this top level entity has a generic MAX_WIDTH
entity counter_N_bit is
  generic (
    MAX_WIDTH : natural := 128
  );
 
-- which this lower level component uses
  counter_slow: counter_slow_N_minus_2bit generic map (
    MAX_WIDTH => 
    MAX_WIDTH  -- this MAX_WIDTH is the same as the MAX_WIDTH defined in counter_N_bit
  )


After taking another look at the code, I'm beginning to wonder if you even wrote this code as just changing the value of MAX_WIDTH of the counter_N_bit will change the design like you seem to want for 126, 64, or 32-bits or anything in between if desired.
 
Last edited:
thankyou ads-ee...
hehe.. its me who wrote this code.. but it doest work as i expected.. it works well without generic mapping to its components... ie when I give the value to the components manually
.
but I am not understanding how to deal with defining this particular part of top module wherein I call a submodule ...

Code: 
	counter_slow: counter_slow_N_minus_2bit [B][U]generic map (128) [/U][/B]
	 port map (        IN_CLK => IN_CLK, -- PIN_ON MODULE => signal_name
		    		IN_EN => sl_enable_slow, -- enable signal after bitwise AND operation of value from the previous counter
				OUT_COUNT_Nminus_2BIT => slv_temp_126_bit -- MSB for the final counter value
				);

In special defining the 128 in the BOLDED part of the code above..
how can I get this value automatically from the generics defined above ?
 

I still don't see what the problem is you've defined the generic MAX_WIDTH with a value of 128.

You should use named association instead of positional e.g.
Code VHDL - [expand]
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counter_slow: counter_slow_N_minus_2bit
  generic map (
    MAX_WIDTH => 128
  ) 
  port map (
    IN_CLK => IN_CLK, -- PIN_ON MODULE => signal_name
    IN_EN => sl_enable_slow, -- enable signal after bitwise AND operation of value from the previous counter
    OUT_COUNT_Nminus_2BIT => slv_temp_126_bit -- MSB for the final counter value
  );


Just had a epiphany...Are you trying to get the value of 128 from the counter_slow: counter_slow_N_minus_2bit generic map (128) to use in your top level? If that is the case you can't do that. Generics don't work from the bottom up. You could add another port to your entity that is assigned the generic value, then you'll have access to the generics value at the top level from the submodules port (caveat, you won't be able to use this port version of the generic as the value of a generic in another module as it will be a signal)
Code VHDL - [expand]
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-- if this is the code at the top level file 
  signal gout : integer;
 
  u_ex: ex  generic map (X =>128)
  port map (
    gout => gout
  );
 
-- this is my ex example code
entity ex is
generic (
  X : integer := 32
)
port (
  gout : out integer
);
end ex;
architecture behave of ex is
begin
  gout <= X;
end behave
 
Last edited:
Hallo Tricky and ads-ee,

I found out the solution. All my issues were to use/call the generic value in the component.

Though I defined it so after few errors I changed it by mistake and was looking for somewhere else.

.
Here is the verified piece of code and that particular line which I was wondering about.

Code: 
counter_slow: counter_slow_N_minus_2bit generic map (MAX_WIDTH)

thank you a lot..

Schones wochenende !!!
 

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