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Circuit problem's after layout design?

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Analog_IC

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When I simulated VCO(in this case ring) using netlist extracted from layout design
, I got to see no oscillation at the out for some of the voltages. say, vco simulated
for 1- 1.8 volt. From 1-1.6 V , no probs, but at 1.7 & 1.8 volt simulation fails. Oscillator doesnot oscillate.
What could happend in layout?, Ofcourse everything was fine before layout.

Thanks
 

Maybe the control voltage is larger. So the dependent current source is larger.
It results that the VCO does not response.
In other words, the frequency of VCO is too large.
 

Thanks, I feel same, but why does it work before layout design. What went wrong in layout so it fails now.
 

check the parasitic capacitance at the output nodes of every stages and compare it to pre-layout capacitance
 

You can try checking the parasitics, but it'll be a nightmare to trace each node's parasitics in your netlist. Or you can try putting capacitors on your prelayout nodes and see if that kills your circuit at 1.7/1.8V.
 

Thanks.
　　　　　As　jiangwp said frequency becomes too high and it fails for higher control voltages. ( looks same reason for fails)
sugesstions about paras caps tried, couldnot work.
Here one more thing is to be noted that generally frequency value of oscillator output is expected lesser than the value had before layout for same control voltage.
BUT in this case I had more value of F (say about 5Mhz) than previous one.
As sugessted IF parasitic cap has increased, I should have reduced output (checked in spice simulation ).

Any help would be appreciated.
 

Analog_IC said:
Thanks.
　　　　　As　jiangwp said frequency becomes too high and it fails for higher control voltages. ( looks same reason for fails)
sugesstions about paras caps tried, couldnot work.
Here one more thing is to be noted that generally frequency value of oscillator output is expected lesser than the value had before layout for same control voltage.
BUT in this case I had more value of F (say about 5Mhz) than previous one.
As sugessted IF parasitic cap has increased, I should have reduced output (checked in spice simulation ).

Any help would be appreciated.
Click to expand...

You shloud double check your simulation test bench. In the real world, after layout you should normaly have a lower frequency then for the schematic only
 

Thanks,
since I m using spice for simulation. So I can only doubt spice simulation file. Netlist is abstracted from layout. Did check spice file, seems no probs.
If I say layout engg. made mistake, then what is it that??
 

Analog_IC said:
Thanks.
　　　　　As　jiangwp said frequency becomes too high and it fails for higher control voltages. ( looks same reason for fails)
sugesstions about paras caps tried, couldnot work.
Here one more thing is to be noted that generally frequency value of oscillator output is expected lesser than the value had before layout for same control voltage.
BUT in this case I had more value of F (say about 5Mhz) than previous one.
As sugessted IF parasitic cap has increased, I should have reduced output (checked in spice simulation ).

Any help would be appreciated.
Click to expand...

Sounds like something is not stable in there. If you tried adding capacitors in the prelayout netlist, and it still works, then it's not due to parasitics. It sounds like you either have a strange connection somewhere or the setup is not right. Check your probes as well.
 

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