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DTA means.. You give a set of test vectors ..for which the simulator caluclates the output values based on available timing information..
ie.. verifying your verilog RTL code by using a testbench and inputs..
You may miss some bugs in ur code if u didnt give a exhaustive or atleast representative set of test vectors..
STA is basically calculating all the delays in the circuit statically and checking whether alll the paths meets your timing requirements like max frequency of operation..
Comparing STA, DTA is mostly for checking the critical-path timing and the multiple-clock-path timing. Like the functional simulation, input test vectors to the DUT, then check the output. Certainly, annotate the SDF in your testbench.
Dynamic means the internal states in a circuit change, then you need input vectors to drive the circuit.
Static means the internal nodes keep unchange in the timing analysis process.
Static timing analysis is used to verify the delays within the design. Using STA, you should verify every path and detect serious problems such as glitches on the clock, violated setup and hold times, slow paths, and excessive clock skew.
Dynamic timing simulation is used for timing analysis of asynchronous designs as well as synchronous designs. Using dynamic simulation the verification can be done to verify the functionality as well as the timing requirements of a design. But it needs to develop comprehensive input vectors to check the timing characteristics of critical paths in a design.
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