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What is a latch-up and how to prevent it?

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lhenfalculan

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What is latch-up? How does it affect the device and how can i prevent it?
 

Re: LATCH-UP

Strictly speaking, latch-up is a process of firing up a parasitic thyristor formed by juctions n+/substaret/nwell/p+.
In a commonly used layout slang, latch-up is a substrate or nwell tie used to prevent the firing up of the parasitic thyristor. This tie prevents the junctions to become forward biased.
 

Re: LATCH-UP

Wow - somebody is still interested in Latchup these days?!!!
Latchup - explanation see MOTOROLA /ON semi HSL databook - there is a simple and nice one. Or description above.
Can be destructive - it is fun to watch when device explodes! Did happen to me few times.
Prevention - the best is space and a lot of substrate ties. No well should be left floating = > a lot of ties. Guardrings work very well.

All is done by careful layout .
 

Re: LATCH-UP

latch up is an effect has the same effect of thyristor which has the property to open without close after cirtain voltage , we can prevent it by puting an epi. layer under deffusion...
SZ
 

Re: LATCH-UP

like scr (positive feedback)

prevent it by guard ring, proper spacing, multiple contacts
 

LATCH-UP

when the layout of pmos&nmos is too close,the latch-up will operate.
 

LATCH-UP

Latch-up is well known nowadays and many text books have described it clearly.

In brief, if large PMOS and NMOS are put TOO closely, the two devices and substrate will form a positive feedback loop and current increases exponentially. Once the devices can't stand with the huge current, they're broken and the circuit fails.
 

LATCH-UP

latch-up is too important in CMOS layout.It wil damage the circuit when it operate.
 

Re: LATCH-UP

The CMOS Technology contains a number of intrinsic bipolar transistors which result in parasitic n-p-n-p processs. They get triggered by the current flowing through the well or substrate and cause shortening of VDD and VSS rails.

To avoid CMOS Latchup, numerous well and substrate contacts are placed close to the source connections of the NMOS/PMOS devices. Also, Guard Rings are placed around such devices.

In recent years, the Latchup is not a problem courtesy to the improved design techniques and process innovations
 

LATCH-UP

when you layout it,you should do it carefully.
 

Re: LATCH-UP

hi
latch up is due to formation of SCR like structure in CMOS.it may damage your circuit if you forget to take step to avoid this formation.for further details Plz refer Weste or Kang you will come to know the basic Machenism and Protection also
 

LATCH-UP

Make sure that the bulk potential is not larger than the source potential.
 

Re: LATCH-UP

TI also has a fantastic write up on latchup and ESD, search TI website
 

Re: LATCH-UP

lhenfalculan said:
What is latch-up? How does it affect the device and how can i prevent it?
it is the phenomina that it pumps noise through substrate into the devices,
it can be avoided by putting no of contacts more on substrate so that it finds
low resistace path
 
Re: LATCH-UP

At Latch up ,there is a path from Supply to VSS which lead to Chip failure .Make sure that Rnwell and Rpsub equal to zero (putting more contacts or use guard rings so that substrate coupling is negligible ) & parasitic bjt would never turn on .
 

LATCH-UP

Latch up happens in CMOS technology, and especially when using high voltage process, such as EEPROM.
 

Re: LATCH-UP

tlihu said:
Latch-up is well known nowadays and many text books have described it clearly.

In brief, if large PMOS and NMOS are put TOO closely, the two devices and substrate will form a positive feedback loop and current increases exponentially. Once the devices can't stand with the huge current, they're broken and the circuit fails.

How much is too close? or How many λ?

Thanks,
tdf
 

LATCH-UP

It depends on process. The distance is function of doping. To form latch-up, the loop of NPN and PNP will be larger than 1. Increasing the distance leads to increase in base width of parasite bipolar. As a result, current gain will be reduce.
 

LATCH-UP

Latchup is malfunctioning of circuit due to parasitic shorting of VDD and Vss. It is due to parasitic SCR formed between PSD,Nwell,Pepi substrate and NSD.
It happens when any one of lateral or vertical (PNP or NPN) is forward biased.
To reduce latchup increase the no of substrate and well ties that will reduce the effective substrate and well resisistance and thereby respective drop.This will prevent forward biasing of transistor.
I hope this will clear this concept.
 

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