Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to create a signal from a file, to be used as a test signal for VHDL testbench?

Status
Not open for further replies.

Fractional-N

Full Member level 1
Joined
Oct 15, 2007
Messages
97
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
2,070
Hi,
is there a way to create an input signal to a VHDL testbench from a HEX file?

also, if you now some useful software that can accept as input a video stream and generate the HEX file from it please tell me
 

1. yes you can. Look into the std.textio package (there are many tutorials on the internet).
2. You may be able to do it with matlab.
 
thanks but i douldn't find any good tutorial. I need to write a testbench in VHDL for Xilinx (Xilinx ISE software). can you please provide me a link?
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top