Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] how to design an analog mux 2:1

Status
Not open for further replies.
D

diaz080

Member level 4
Joined
Oct 3, 2012
Messages
73
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,714
need to design an analog mux made using transistor to pass 1,-1v with respect to clk in cadence . I used logic gates to make the digital mux which is able to pass 1,0 .
But when it comes to -ve value of i/p it is not working..any idea?
 

can u please explain ?

- - - Updated - - -

Screenshot.pngwave.png
used simple transmission gate ..but output is not as desired
 

That is only half a transmission gate - try adding the other half (PMOS).

Keith
 
That is only half a transmission gate - try adding the other half (PMOS).
Click to expand...
In some cases, a single transistor might work, it's a matter of signal and supply voltage ranges. You need complementary transistors in transmission gates to achieve a rail-to-rail signal voltage range.

Referring to the circuit in post #3, the input signal must not swing beyond the MOSFET substrate voltage range.
Basic rules of CMOS design must be observed.
 
wave (1).pngd.png

see output is touching +1v..but not -1
 

That is only half a transmission gate - try adding the other half (PMOS).
Click to expand...
Yes, problem of substrate voltage, as said. Plot input current to see what happens.
 
FvM said:
In some cases, a single transistor might work, it's a matter of signal and supply voltage ranges. You need complementary transistors in transmission gates to achieve a rail-to-rail signal voltage range.

Referring to the circuit in post #3, the input signal must not swing beyond the MOSFET substrate voltage range.
Basic rules of CMOS design must be observed.
Click to expand...

Sorry, I didn't notice the minus signs in the simulation results. Sometime QVGA screens just aren't big enough!

I sometimes only use one transistor for a transmission gate when I can be certain of the input voltage range.

Keith
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top