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VHDL - connection std_logic_vector with array of std_logic_vector

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wsch

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Hi

I have a type:

Code: 
noc_io_data is array (natural range <>, natural range <>) of std_logic_vector (SIZE dowto 0);

that I need to connect with a:

Code: 
std_logic_vector

How can I do this connection? Only with the assignment of the individual bits from the array to the vector?

What syntax should I use?

Thanks
 

You have an ARRAY of vectors that you are trying to 'connect' to a single vector? I'm not sure what you want, but I THINK you might want something like this:

Code: 
signal a:std_logic_vector(size downto 0);
signal x,y:natural;
.
.
a<=noc_io_data(x,y);
 

Please post the code that you cant get to work - its quite difficult to speculate.
 

I need to connect these components:

Code: 
entity wrapper is        
    port( 
      clock_i                : in  std_logic;
      reset_i                 : in  std_logic;
      noc_addresses_i  : in  std_logic_vector ((FLIT_SIZE/2) * n_ag_g-1 downto 0);
      data_i                  : in  std_logic_vector (FLIT_SIZE * n_ag_g-1 downto 0);   
      data_o                 : out std_logic_vector (FLIT_SIZE * n_ag_g-1 downto 0);            
      data_avail_i          : in  std_logic_vector (n_ag_g-1 downto 0);  
      data_avail_o         : out std_logic_vector (n_ag_g-1 downto 0);        
      credit_i                 : in  std_logic_vector (n_ag_g-1 downto 0);
      credit_o                : out std_logic_vector (n_ag_g-1 downto 0)    
    );
 end wrapper;


entity network is
	port(
		clock_i         : in  std_logic;
		reset_i         : in  std_logic;
		noc_addresses_i : in  noc_io_address(NOC_SIZE_X-1 downto 0, NOC_SIZE_Y-1 downto 0); 
		data_i          : in  noc_io_data(NOC_SIZE_X-1 downto 0, NOC_SIZE_Y-1 downto 0, FLIT_SIZE-1 downto 0);   
		data_o          : out noc_io_data(NOC_SIZE_X-1 downto 0, NOC_SIZE_Y-1 downto 0, FLIT_SIZE-1 downto 0);    
		data_avail_i    : in  noc_io_bit(NOC_SIZE_X-1 downto 0, NOC_SIZE_Y-1 downto 0); 
		data_avail_o    : out noc_io_bit(NOC_SIZE_X-1 downto 0, NOC_SIZE_Y-1 downto 0); 
		credit_i        : in  noc_io_bit(NOC_SIZE_X-1 downto 0, NOC_SIZE_Y-1 downto 0); 
		credit_o        : out noc_io_bit(NOC_SIZE_X-1 downto 0, NOC_SIZE_Y-1 downto 0); 	
	);
end network;

Here is the types definitions:

Code: 
type noc_io_bit is array(natural range<>, natural range<>) of std_logic;
type noc_io_address is array(natural range<>, natural range<>) of std_logic_vector((FLIT_SIZE/2)-1 downto 0);
type noc_io_data is array(natural range<>, natural range<>) of std_logic_vector(FLIT_SIZE-1 downto 0);
 

Sorry, but this is not making any sense to me. You've got inputs in both entities that have 'similar' dimensions, and outputs in both entities that have similar dimensions. Are you trying to connect inputs to inputs and outputs to outputs?
 

Hi

I have a wrapper that I use to send and receive data to/from network.
This wrapper use std_logic_vector and I do not want to modify it.
I also do not want to modify the input interface of network.
So, how can I connect these components?
Only with the assignment of the individual bits from the array to the vector? What syntax should I use?
 

Looking at your code, your noc_io_data type doesnt match the usage (the type has 2 dimensions, but you size 3 in the port definition

For this, you will need to write a custom conversion function that converts your large std_logic_vectors into a 2D array of std_logic_vectors and/or vice versa

probably something like this:

Code VHDL - [expand]
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function 2d_to_1d_slv(slva : noc_io_data) return std_logic_vector is
  variable slv : std_logic_vector(slv'length(1) * slv'length(2) * FLIT_SIZE -1 downto 0);
begin
  for i in slva'range(1) loop
    for j in slva'range(2) loop
      slv( i*(j+1)*FLIT_SIZE -1 downto i*j*FLIT_SIZE ) := slva(i,j);
    end loop;
  end loop;
 
  return slv;
end function 2d_to_1d;
 

I try to convert std_logic_vector into a 2D array

Code: 
gen_connections_x: for i in 0 downto NOC_SIZE_X-1 generate
		gen_connections_y: for j in 0 downto NOC_SIZE_Y-1 generate

			-- Split std_vector from input interface into arrays
			noc_addresses_is(i,j) <= noc_addresses_i((i*NOC_SIZE_X*(FLIT_SIZE/2)+(j*(FLIT_SIZE/2))) downto (i*NOC_SIZE_X*(FLIT_SIZE/2)+(j*(FLIT_SIZE/2))) + FLIT_SIZE/2 - 1);
			data_is(i,j) <= data_i((i*NOC_SIZE_X*FLIT_SIZE + j*FLIT_SIZE) downto (i*NOC_SIZE_X*FLIT_SIZE + j*FLIT_SIZE + FLIT_SIZE - 1));
			data_avail_is(i,j) <= data_avail_i((i*NOC_SIZE_X + j));
			credit_is(i,j) <= credit_i((i*NOC_SIZE_X + j));

			-- Join internal arrays into output interface std_vectors
			data_o((i*NOC_SIZE_X*FLIT_SIZE + j*FLIT_SIZE) downto (i*NOC_SIZE_X*FLIT_SIZE + j*FLIT_SIZE + FLIT_SIZE - 1)) <= data_os(i,j);
			data_avail_o((i*NOC_SIZE_X + j)) <= data_avail_os(i,j);
			credit_o((i*NOC_SIZE_X + j)) <= credit_os(i,j);	
					
		end generate gen_connections_y;
	end generate gen_connections_x;

But I still get this error:

(vcom-1390) Too many indices (3) for array type work.hermes_pld_package.noc_io_data (dimensionality 2).
 

You dont point out where the error is pointing to. I suspect, Like I said, in the code you origionally posted, the data_i and data_o ports have 3 dimensions when the type declaration only has 2.
 

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