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How to improve the bias stability in LAYOUT ?

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twonsr

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Dear all :

If I have already finished my design to provide a stable voltage reference bias to nmos and pmos , but I want to put some mos capacitors between VDD and pmos bias or between nmos bias and gnd in the layout.

I don't know if this way will works , and I have no idea if this way will bring what performance damage ?

Any suggestion for me is welcome.

TKS
 

Maybe the current bias for other cicuit is better than voltage .

Specifically the current bias is the best for long distance bias on a system chip.

The bypass capacitor of VDD and VSS is very important in bias . But u must select a right value because it work as a filter. if its value is right, it will not damage circuit performance.
 

the capacitor can filter the high frequency noize.small capacitor can also fast the load's transient action.
 

I believe it will work.
But you have to make sure that the pmos and nmos turn on
Besides you have to check if the inserted cap introduce another loop
 

Do take note of how you hook up the MOS-caps. If the voltage across the caps is smaller than Vt, you may want to put the MOS-caps in accumulation mode instead to get a better fF/um2.
 

usually the decoupling caps for the supplies are off chip, I don't understand why would you want to layout these caps on IC.
 

From my experience, I think you could put them in you chip as more as possible.
 

structer decide function,don't need the exact only one operation point,just for good structer of bias circuit.
 

chinito said:
usually the decoupling caps for the supplies are off chip, I don't understand why would you want to layout these caps on IC.
Click to expand...

True, there are some big decoupling caps for power supply off chip;
at the same time there are also some on-chip decoupling caps.
They coexist for stabilizing power supply and reducing power spikes at different regions/frequency range.

regards,
jordan76
 

Should be good enough to just add a couple of PMOS transistors with S,D,Well tied to supply and gate tied as capacitor. Same for a couple of NMOS tarnsistor S,D,bulk tied to GND gate tied to line. This is very common in band gap layouts.
 

Hello all:
Which block will ocuppy this bias circuit is another issue. The length of the mos depend on ur appication blocks.
 

Stability shouldn't be a problem, but you'll effectively kill the circuit's psrr.
 

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