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How the task is being called

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Muthuraja.M

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In verilog how the task of one module is called by another module ?


I used `include "test.v" ....

But its not working ...


Pls give me suggestions..

Thanks in advance...
 

Assumpt the instance name of the module including task is DUT1, and the task name is "test_tsk", you can use "higher_hierarchy".DUT1.test_tsk to call this task. If there's assignment in the task, the calling only can change signal define in DUT1. Hope it's helpful.
 

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