electrosam
Newbie level 3
Hello
I am trying to learn UVM and I recently developed environment for a simple D Flip Flop.
Earlier, I did it for simple AND Gate.
I have a monitor in the agent environment which prints inputs given to the DUT and also outputs coming out of DUT.
For AND gate example, monitor worked just fine. It showed inputs and outputs both correctly.
When I modified the environment for D Flip Flop it did not work properly.
In Questa wave window, I added all signals for DUT and that of Virtual Interface. I observed that DUT behaves properly, the output q latches data on each posedge and holds it stable until next posedge.
However the q in Virtual Interface does not stay stable. It shows only a glitch at posedge if d input is 1.
I have declared q as logic q in the interface and bit q in Transaction.
Basically DUT signals and VI signals for VI match but they do not match for DFlop.
Q.1- Should output from DUT be declared in transaction or not ?
Q.2 - Is there only one transaction class or multiple for single design ?
Q.3 - Why Virtual Interface q signal is not staying stable for me ?
Attached-
1.Screenshot UVM AND Gate which is in order
2. Screenshot of UVM DFlop which is having issues
3. ZIP containing UVM source code for AND Gate (Compile all SV and run top block)
4. ZIP containing UVM source code for D Flip Flop (Compile all SV and run top block)
Looking forward for help !
Thank You !
I am trying to learn UVM and I recently developed environment for a simple D Flip Flop.
Earlier, I did it for simple AND Gate.
I have a monitor in the agent environment which prints inputs given to the DUT and also outputs coming out of DUT.
For AND gate example, monitor worked just fine. It showed inputs and outputs both correctly.
When I modified the environment for D Flip Flop it did not work properly.
In Questa wave window, I added all signals for DUT and that of Virtual Interface. I observed that DUT behaves properly, the output q latches data on each posedge and holds it stable until next posedge.
However the q in Virtual Interface does not stay stable. It shows only a glitch at posedge if d input is 1.
I have declared q as logic q in the interface and bit q in Transaction.
Basically DUT signals and VI signals for VI match but they do not match for DFlop.
Q.1- Should output from DUT be declared in transaction or not ?
Q.2 - Is there only one transaction class or multiple for single design ?
Q.3 - Why Virtual Interface q signal is not staying stable for me ?
Attached-
1.Screenshot UVM AND Gate which is in order
2. Screenshot of UVM DFlop which is having issues
3. ZIP containing UVM source code for AND Gate (Compile all SV and run top block)
4. ZIP containing UVM source code for D Flip Flop (Compile all SV and run top block)
Looking forward for help !
Thank You !
