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following error during post synthesis simulation using NCSIM tools

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alokkmr18

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ERROR : ncelab: *E,MTOMDU: More than one unit matches 'worklib.whole_digital_tdc_ckts':
whole_digital_tdc_ckts is my netlist genearted file in vhdl after synthesis process using design complier(synopsys tool)
one more ques..is it necessary to include sdc file for post synthesis smulation
 
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