Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] static timing analysis

Status
Not open for further replies.
J

jigs047

Junior Member level 1
Joined
Apr 8, 2013
Messages
17
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Location
Ahmedabad, India, India
Activity points
1,367
there are two type of static timing analysis. pre STA and post STA. so ,how do this using sysnopsys tool?
 

STA means static timing analysis, then you could analyze your design at any time of the flow. Generally the STA is only done as final step to check everything is fine.
 

Pre STA is done by Design Compiler and is done before PnR..
and Post STA is done by Prime Time and is done on Post layout netlist....

But I can't understand that how we can do Pre STA as there is not any interconnection wire length information.
 

maulin sheth said:
But I can't understand that how we can do Pre STA as there is not any interconnection wire length information.
Click to expand...

Therefore, the timing analysis will be more accurate after post STA.
But we will try to estimate the interconnection delay before layout stage, said topographical mode in Design Compiler.
This will reduce the gap between the pre STA and post STA.
 

maulin sheth said:
Pre STA is done by Design Compiler and is done before PnR..
and Post STA is done by Prime Time and is done on Post layout netlist....

But I can't understand that how we can do Pre STA as there is not any interconnection wire length information.
Click to expand...

Wireload and interconnect are modelled in pre layout stage and .libs are used to compute the timing. Post layout the actual RC values are taken into account for accurate analysis.
 

jeevan.life said:
Wireload and interconnect are modelled in pre layout stage and .libs are used to compute the timing. Post layout the actual RC values are taken into account for accurate analysis.[/QUOTE

what is the format for wire load model?as u said that it can be found in .lib file.so, will you please tell that how wire load model looks like?
please gave me example.
Click to expand...
 

Wire load is a library file...and the format is .lib and also .db.... and .lib is ASCII format and .db is Binary format...
It will include the wire load model...which contain the unit capacitance, fanout length etc....
 

maulin sheth said:
Wire load is a library file...and the format is .lib and also .db.... and .lib is ASCII format and .db is Binary format...
It will include the wire load model...which contain the unit capacitance, fanout length etc....
Click to expand...

will please explain how wire load model look like? i have seen .lib file but i unable to find this wlm.
 

You can use "report_lib lib_name " command in dc_shell. It should report wire load model too.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top