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computer architecture questions

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abd93

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I need some help,,,can
For the following code:assuming an un-pipelined processor :

MUL AX, BX, CX Number of Stages=
OR EX, BP, AX Number of Stages=
Load DX, 0 (CX) Number of Stages=
Load EX, 0 (DX) Number of Stages=
ADD DX, DX, EX Number of Stages=
Store DX, 1 (CX) Number of Stages=
Store EX, 1 (DX) Number of Stages=
 

Come on, for homework assignments at least pretend to cut-n-paste the assignment in a readable fashion. I guess this one gets this weeks award for least amount of time spent on a "Do my homework post". Well done!
 
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    abd93

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For the following code:
MUL AX, BX, CX
OR EX, BP, AX
Load DX, 0 (CX)
Load EX, 0 (DX)
ADD DX, DX, EX
Store DX, 1 (CX)
Store EX, 1 (DX)
assuming an un-pipelined processor.what is the number of stages for each instruction?
 

Looks like Intel code, however they have made more than one type of CPU (or maybe your Teacher doesn't know that :) )

Check out the 'manuals' at the bottom of the Wikipedia page below for current CPU architecture ..
Source(s):
https://en.wikipedia.org/wiki/X86_assembly_language


I am sure you can appreciate the reciprocity of effort here. Took me ages! You multi-sourcing laz^H^H^H person that displays qualities that one might consider not exactly positive.
 

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