What is the Clock Latency,Network Latency,Source Latency,Insertion Delay?

Hello Every one

may i know the difference between

1.Clock Latency
2.Source Latency
3.Network Latency
4.Insertion Delay





Thanqs in Advance.........


RGR

Clock latency is the delay between the clock source and the clock pin. It is dependant on hardware, PCB, traces, etc. Simply, Clock latency means, the number of clock pulses required by the ckt to give out the first output. Clock latency is the combination of source latency and network latency.

Source latency is the propagation delay from the origin of the clock to the clock definition point (for example, a clock port).

Network latency is a measure of how fast a network is running. The term refers to the time elapsed between the sending of a message to a router and the return of that message (even if the process only takes milliseconds, slowdowns can be very apparent over multi-user networks).

Insertion delay is otherwise called Clock Latency.

Clock Network latency: the delay from source of the clock (the pin or port in constraints where the clock is defined on) to a sink (a flop's clock pin), when the term is used specific to a sink. When network latency is used in general on a certain clock, it means the "average" delay from the source of the clock to all its sinks.
Clock network latency is useful in controlling the behavior of optimization during pre-clock-tree stages, in constraint command: set_clock_latency. It can be used to model the clock insertion delay or skew that will occur after building the tree ahead of time. Let's say setup time to enable pin of a clock-gating component is critical. Defining a negative network latency on the clock pin of the clock-gating component with respect to its clock with tell the tool to work harder on the path to the enable pin during pre-clock-tree optimization stages. Once the tree is built and the real insertion delay is calculated, network latency defined in constraints is discarded.
Clock Source latency: is the delay from the actual source of the clock (maybe off chip or off-block) to the node where the clock is defined in the constraints: set_clock_latency 0.4 -source [get_clocks clk1]. Clock Source Latency can be used to model off-chip clock latency when a clock generation circuit is not part of the current design. Also, for generated clocks,
clock source latency can be used to model the delay from the master clock to the generated clock definition point.
Clock Insertion delay: it is referred to the actual clock delay after clock tree is built. No more modeling of the potential delay. It is the calculated delay. The term is usually used more specifically; insertion delay from where to where.

See this post. It will answer everything!! https://vlsi-soc.blogspot.in/2013/04/clock-jargon-important-terms.html