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[SOLVED] Timing violation warnings in gate-level simulation

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Hanul

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Hello,

I've got an warning message as follows during gate-level simulation with NCVerilog.

Warning! Timing violation
$width( posedge CLK &&& (RSTB == 1'b1):135 PS, : 136 PS, 110 : 110 PS );
File: /usr/eda/synopsys/lib/SAED_EDK90nm/Digital_Standard_Cell_Library/verilog/saed90nm.v, line = 4812
Scope: tb_xxx.abc_reg_0_
Time: 136 P

I'd like to know why this warning happened and also how to solve.

It would be a big help for me if someone recommend me a good reference for solving this problem.

Thank you in advance.
 

Well, if your STA is clean and you have a netlist simulation error, two solutions, you have some false paths which mask your sta, or the case is not " real" in your simulation.
 

Hello Hanul,

I also got this type of warning, but I am not getting any simulation mismatch.So in that case, we don't need to worry.
But if you got the simulation mismatch due to this warning and width violation,thn need to create SDF again.
 

I missed `timescale directive...........

Now it's working.

Thank you for your replies.
 

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