Custom IP core with fixed point

Hi,

I wanted to create IPCore to add two fixed point .
I added fixed_pkg file to pcores\add_fix_v1_00_a\hdl\vhdl .
first I wrote in entity :
port(
reg_out : out sfixed(29 downto -2);
.
.);

and in architecture I wrote process

fix: process(slv_reg0,slv_reg1)

variable reg0,reg1,reg2 : (29 downto -2);
begin
reg0:=to_sfixed(slv_reg0,C_SLV_DWIDTH);

reg1:=to_sfixed(slv_reg1,C_SLV_DWIDTH);
reg2:=reg1 + reg0;
reg_out <=reg2;
end process fix;

when I wanted to import it

Errors:

D:\Labs\ipcore\pcores\add_fix_v1_00_a\hdl\vhdl\user_logic.vhd" line 151.

to_sfixed can not have such operands in this context.

D:\Labs\ipcore\pcores\add_fix_v1_00_a\hdl\vhdl\user_logic.vhd" line 152.

to_sfixed can not have such operands in this context.

EDK:2121-Parse Errors encountered in HDL source

Warning:EDK:3590- Unable to detect temporary project file.


what are the steps to overcome this errors ?

Thanks in advance

adam_lo said:

Hi,

I wanted to create IPCore to add two fixed point .
I added fixed_pkg file to pcores\add_fix_v1_00_a\hdl\vhdl .
<snip>
what are the steps to overcome this errors ?

Thanks in advance

Click to expand...

- Start by reading the user's guide.
- Then read the parameter types for the 'to_sfixed' function that you are calling and make sure that you are passing in the correct types

I'm assuming that your 'slv_*' signals are std_logic_vectors which implies that you have not done either of the above two points since std_logic_vectors have no numeric interpretation (unlike signed, unsigned, sfixed, ufixed, etc.)

Kevin