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Not so much being able to read the counter at 'all' time, but just the ability to read the full counter at all. If there are known gaps in time when the counter won't be counting for a long enough period of time, then the count eventually will stabilize and can be read.
The other thing that will limit the speed in an FPGA environment is that the clocks for the flip flops will be routed using general purpose routing so the performance might not be so hot. Whether that is the limiting factor in a particular case would depend on the specific part that is chosen.
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