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vhdl multiplier 4 bit by 4 bit design with shift registers

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vhdl34

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hi im trying to make a mmultilier of 4 bit by 4 bit here under is my code however i have some problems as its not working. it diviide the program in two clock cycles by the state however the program is not changing any type of help is reallyy appreciated thanks
Code: 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_misc.all; 
use IEEE.std_logic_unsigned.all; 

entity multiply is
  port(clk :in std_logic;
     
      multiplicand_in : in std_logic_vector(3 downto 0);
      multiplier_in : inout std_logic_vector(3 downto 0);
      
      result: out std_logic_vector(7 downto 0));
end multiply;

Architecture multiply_arch of multiply is
  begin 
  
    process(CLK)
        
        variable temp : std_logic_vector(7 downto 0):= "00000000";
        variable counter : std_logic_vector(3 downto 0) := "0000";
        variable state : std_logic:='0';
       begin
           
    
    if (CLK'EVENT and CLK = '1') then
         if (counter <= "0100" ) then
           
           
            if (multiplier_in(0) = '1') then
             temp := temp + multiplicand_in ;
              elsif(multiplier_in(0) = '0') then
               temp := temp +"0000";
      
             end if; 
           
                

  counter := counter + "0001";
  multiplier_in <= '0' & multiplier_in(3 downto 1); 
  result <= temp;
  end if;
end if;
    end process;
    end multiply_arch;
 

What is the state variable for? it isnt in the code.
Why is multiplier in an inout? You have no tri-state driver for this signal internally, so if you drive it externally you will get "XXXX". You should use an internal signal.
 

thanks but i having a problem with the counter im assigning the counter to "0000" and add "0001" however the counter is ahving a value of "1000" in the beginning of the program what can be the mistake and i have another question is the syntax correct
Code: 
variable reg : std_logic_vector(3 downto 0) := multiplier_in;
 

Have you got a testbench? are you running this in simulation? Please post the testbench code.

Second - your syntax - you cannot initialise a variable or signal from another variable or signal - is has to be a constant.
 

hi, i realized what the problem was. however i cant really rearrange it in order to make this work i need to shift the multiplier to the right and the multiplicand to the left on every clock cycle however i cannot make it can you help me to do that pls. i updated my architecture and tb these are here under
tb
Code: 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_misc.all; 
use IEEE.std_logic_unsigned.all;
 
entity multiplier_tb is
  port(multiplier :out std_logic_vector(3 downto 0);
    multiplicand :out std_logic_vector(3 downto 0);
     CLK_out : out std_logic);
     
   end multiplier_tb;
   
architecture multiplier_tb_arch of multiplier_tb is
begin 
  operation_1 : Process 
   begin 
   
    
  
      wait for 0 ns ; multiplier<= "1101";
      wait;

    end process operation_1;

  
   
   operation_2 : process
    begin
      wait for 0ns ; CLK_out <= '0';
      wait for 10 ns; CLK_out<= '1';
      wait for 10 ns; CLK_out <= '0';
 end process operation_2;

   
   operation_3 : process
   begin
     
    wait for 0ns ; multiplicand <="1011";
    wait;
     end process operation_3; 
      end multiplier_tb_arch;
architecture
Code: 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_misc.all; 
use IEEE.std_logic_unsigned.all; 

entity multiply is
  port(clk :in std_logic;
     
      multiplicand_in : in std_logic_vector(3 downto 0);
      multiplier_in : in std_logic_vector(3 downto 0);
      
      result: out std_logic_vector(7 downto 0));
end multiply;

Architecture multiply_arch of multiply is
  begin 
  
    process(CLK)
        
        variable temp : std_logic_vector(7 downto 0):= "00000000";
        variable reg : std_logic_vector(3 downto 0) := "1101";
        variable reg1 : std_logic_vector(7 downto 0) := "00000000";
        variable counter : std_logic_vector(3 downto 0) := "0000";
        variable state : std_logic:='0';
        
       begin
           
    
    if (CLK'EVENT and CLK = '1') then
         
           
          if(counter <= "0100")then
          
           
            if (reg(0) = '1') then
             temp := temp + multiplicand_in ;
             reg := '0' & reg(3 downto 1);
           
              elsif(reg(0) = '0') then
               temp := temp +"0000";
                reg := '0' & reg(3 downto 1);
               
             end if; 
          
      
                
counter := counter + "0001";
 
  
   
  result <= temp;

   end if; 
end if;
    end process;
    end multiply_arch;
         

[CODE]
 

Why does your testbench have ports? why dont you instantiate the multiplier inside the testbench?
 

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