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verilog error in programming???

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mohi@608

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Code: 
module counter(input [31:0] baud_rate_req,input [31:0] sys_freq,input clk,input reset,output [31:0] count_out);
reg [31:0] count_value;
count_value =(sys_freq/baud_rate_reg);
always@(posedge clk or negedge reset)
begin
if(reset==1)
count_out=32'b0;
else
while(count_out<count_value)
count_out=count_out+32'b1;
end
endmodule

Code: 
rfs@rfs-virtual-machine:~/brg$ vlog counter.v 
Model Technology ModelSim SE vlog 6.5b Compiler 2009.05 May 21 2009
-- Compiling module counter
** Error: counter.v(7): near "=": syntax error, unexpected '='
rfs@rfs-virtual-machine:~/brg$ gvim counter.v

i am not able to identify the error ????
 

Try with this code and let me know.
########################################
module counter(input [31:0] baud_rate_reg,input [31:0] sys_freq,input clk,input reset,output [31:0] count_out);
wire [31:0] count_value;
assign count_value =(sys_freq/baud_rate_reg);

reg [31:0] count_out_int;
always@(posedge clk or negedge reset)
begin
if(reset==1)
count_out_int=32'b0;
else
while(count_out_int<count_value)
count_out_int=count_out_int+32'b1;
end

assign count_out = count_out_int;

endmodule
#################################################
 

mail4idle2 said:
assign count_value =(sys_freq/baud_rate_reg);
Click to expand...

Even with the assign, unless baud_rate_reg is a constant or some power of 2 synthesis tools won't synthesize a divider.

-alan
 

synthesis tools won't synthesize a while loop too.

moreover

count_out_int=32'b0;
else
while(count_out_int<count_value)
count_out_int=count_out_int+32'b1;
end

hei dont u think at the end the value of count_out_int will be equal to count_value ?????

Then wat is the use of this code snippet???
 

Why we are talking about synthesis.
His question was compilation issue.

Do not confuse with extra information.
 

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