daisordan
Newbie level 6
Hi, I have learnt how to use system verilog but this is my first time to use verilog. So I have a question about how to use 2 condition in assign.
I have 3 input (a,b,c) and 1 output (z)
For System verilog, I will do it like that:
Thanks for the help
Ivan
I have 3 input (a,b,c) and 1 output (z)
For System verilog, I will do it like that:
For verilog: //this is doing the first part of function, how can I put the second part into this assign?always_comb //always_comb is the same function as assign
begin
if(a==b)
z=a;
else
if (b==c)
z=b;
end
assign z = (a & b) ? a:z; //I know thats wrong since a=/=b , this will output z for z. What should I write if a=/=b, it will do " if (b==c)
z=b;
Thanks for the help
Ivan
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