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[SOLVED] Bit slicing problem in VHDL

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n_sanjay_n

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Hi,
I have written a comparator using bit slicing in VHDL. The code basically takes 2 vector inputs A and B, compares them and gives output C=A if A>B or else C=B. To do this, I first wrote a 1 bit comparator :

Code VHDL - [expand]
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entity bit_slice is
port (
    A, B, Eq_in, Gt_in : in  std_logic;
    Eq_op    : out std_logic;
    Gt_op : out std_logic);
end bit_slice;
 
architecture arch_bit_slice of bit_slice is
begin
  process (A, B, Eq_in, Gt_in)
    begin
Eq_op <= (A xnor B) and Eq_in;
if(Gt_in = '1') then
Gt_op <= '1';
else
Gt_op <= (Eq_in) and (A and (not(B)));
end if;
end process;
end arch_bit_slice;


I want to use this in a generic width comparator and I wrote a code for the same. There are no errors in the code but the output is not as expected. In the program code below, I have instantiated the previous program and used the generate keyword to replicate it n times.

Code VHDL - [expand]
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entity prob is
  
  generic (
    n : integer := 3);
 
  port (
    A, B : in  std_logic_vector((n-1) downto 0);
    C    : out std_logic_vector((n-1) downto 0)
    );
    
    end prob;
 
architecture arch_prob of prob is
component bit_slice 
  port (
    A, B, Eq_in, Gt_in : in  std_logic;
    Eq_op    : out std_logic;
    Gt_op : out std_logic);
end component;
 
signal t_Eq_in : std_logic_vector ((n) downto 0);
signal t_Gt_in : std_logic_vector ((n) downto 0);
signal t_Eq_op : std_logic_vector ((n) downto 0);
signal t_Gt_op : std_logic_vector ((n) downto 0);
signal temp : std_logic;
 
begin
prob2_gen : for i in (n-1) to 1 generate
  begin
  t_Eq_in(t_Eq_in'high) <= '1';
  t_Gt_in(t_Gt_in'high) <= '0'; 
 
 Ai: bit_slice port map
 (
 A => A(i),
 B => B(i),
 Eq_in => t_Eq_in(i),
 Gt_in => t_Gt_in(i),
 Eq_op => t_Eq_op(i-1),
 Gt_op => t_Gt_op(i-1));
 
 end generate prob_gen;
 
 temp <= t_Gt_op(t_Gt_op'low);
  process(temp)
    begin
  if(temp = '1') then
 C <= A;
 else
 C <= B;
 end if;
 end process;
  
 end architecture;


Here is the test bench (just in case):

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
entity tb_bit_slice is
  end tb_bit_slice;
 
architecture arch_tb of tb_bit_slice is
 
component prob
  generic (
    n : integer);
 
  port (
    A, B : in  std_logic_vector((n-1) downto 0);
    C    : out std_logic_vector((n-1) downto 0)
    );
end component;
 
  constant n_tb : integer := 3;
  signal t_A, t_B, t_C: std_logic_vector((n_tb-1) downto 0);
 
begin
 
    U1 : prob
      generic map (n_tb)
      port map ( t_A, t_B, t_C);
 
    test_process : process
    begin
     
      t_A <= "100";
      t_B <= "000";
      wait for 100 ns;
 
      t_A <= "001";
      t_B <= "010";
      wait for 100 ns;
 
      t_A <= "110";
      t_B <= "001";
      wait for 100 ns;
 
      t_A <= "000";
      t_B <= "110";
      wait for 100 ns;
 
      t_A <= "101";
      t_B <= "100";
      wait for 100 ns;
 
      t_A <= "111";
      t_B <= "111";
      wait for 100 ns;
 
      wait;
 
    end process;
 
end arch_tb;
 
Last edited by a moderator:

How about telling us what you expect, and what you got.
 

Not sure I quite follow the logic, but line 16 of your bit slice will produce a '1' (greater than, I presume) ONLY if the Eq_in input is '1'. I'm assuming the Eq_in input would only be '1' if the preceding bits are all equal, is that correct? If so, then the logic is wrong.

For example, if you have A=1011 and B=0100, then the Eq_in signal for the 4th bit would be '0' (since 011 /= 100). And even though the "(A and (not(B))" ==>'1`, Gt_op would still be '0'.

But maybe I misunderstand the whole thing.
 

When you use A = 1011 and B = 0100, if all works well, since we are checking from the MSB, the output will be a zero for both Eq_op (equal?) and Gt_op (greater than?) bit.

As for the first part, I basically want it to work this way:
if A = 1011 and B = 1010. In this case, bit_slice will give an output of Eq_op = 1 all the way until the third module. At the fourth module, it turns out that A>B. Here, it then checks if the previous bits are equal. In this case, since both are 101, the Eq_op will be a high and hence, the Gt_op will go high.
This indicates that A>B.
Now, my problem is that I want to use the "generate" keyword to generate multiple instances of bit_slice to do the aforementioned operation for any number of bits.

What I got: bit_slice works for a single bit. Upon trying to replicate the same for multiple bits, the output is a high impedance.
What I want to know: How do I use the generate statement for replicating bit_slice, as the equal and greater outputs bits of one module are the inputs for the next module.

Thanks for the help! :)
 

You wont have a high impedance output - I dont see any tri-state buffers in your design - high impedance is marked with 'Z'. Do you mean just logic '1'? If you are getting high impedance, then the problem is not in the code you posted.

There is nothing wrong with your code syntactically, so I assume the problem is an architectural one - this is where you should be testbenching.

The main question is why are you doing this such long winded method? whats wrong with the functionion:

if a > b then
 
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Reactions: FvM

    FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating
Nicely hidden bugs... :smile:

Try this:
Code: 
signal t_Eq : std_logic_vector ((n-1) downto 0);
signal t_Gt : std_logic_vector ((n-1) downto 0);
signal temp : std_logic;
 
begin
  t_Eq(n-1) <= '1';
  t_Gt(n-1) <= '0'; 
  prob2_gen : for i in 1 to n-1 generate
 Ai: bit_slice port map
 (
 A => A(i),
 B => B(i),
 Eq_in => t_Eq(i),
 Gt_in => t_Gt(i),
 Eq_op => t_Eq(i-1),
 Gt_op => t_Gt(i-1));
 
 end generate prob2_gen;
 
 temp <= t_Gt(0);
 process(temp,A,B)
...
 
@TrickyDicky
Thanks for the help! Well, the "long winded method" is necessary because I want this design to be implemented in a chip that I'm designing. To do that, I have to be able to basically create a cell like structure not only in VHDL, but also in the CAD tool I use. I use Magic design tool and I want to be able to create a single module of "bit_slice" so I can just replicate it as many times I want. The advantage of doing so is that I need to properly optimize only one block and all the others will be the same.
There are a bunch of reasons more which I can tell you if you are interested in them!

- - - Updated - - -

@TrickyDicky
Thanks for the help! Well, the "long winded method" is necessary because I want this design to be implemented in a chip that I'm designing. To do that, I have to be able to basically create a cell like structure not only in VHDL, but also in the CAD tool I use. I use Magic design tool and I want to be able to create a single module of "bit_slice" so I can just replicate it as many times I want. The advantage of doing so is that I need to properly optimize only one block and all the others will be the same.
There are a bunch of reasons more which I can tell you if you are interested in them!

- - - Updated - - -

FvM said:
Nicely hidden bugs... :smile:

Try this:
Code: 
signal t_Eq : std_logic_vector ((n-1) downto 0);
signal t_Gt : std_logic_vector ((n-1) downto 0);
signal temp : std_logic;
 
begin
  t_Eq(n-1) <= '1';
  t_Gt(n-1) <= '0'; 
  prob2_gen : for i in 1 to n-1 generate
 Ai: bit_slice port map
 (
 A => A(i),
 B => B(i),
 Eq_in => t_Eq(i),
 Gt_in => t_Gt(i),
 Eq_op => t_Eq(i-1),
 Gt_op => t_Gt(i-1));
 
 end generate prob2_gen;
 
 temp <= t_Gt(0);
 process(temp,A,B)
...
Click to expand...

Hi, Thanks for that. I don't know if its a co-incidence, I actually logged into Edaboard just to post the exact same solution I got myself today :-D! Thanks for the help though ant by the way, I think that matrices t_Eq and t_Gt must be n downto 0 because they have to have an extra bit when compared to A and B.
 

I think that matrices t_Eq and t_Gt must be n downto 0 because they have to have an extra bit when compared to A and B.
Click to expand...
No. It's unused in the code respectively erroneously initialized but never read (in your original code).

I understand that the exampe is just an excercise for bit-slice and generate constructs. IMHO there's nothing to optimize in the trivial compare case.

Although the problem is pretty simple, the code is complex enough to hide a basic bug in a way, that it's overlooked by several VHDL practioneers at first sight (me too).
 

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