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In what applications, low-Vth MOSFET and medium-Vth MOSFET are useful?

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Ziqi

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Hi, all.
Low-Vth MOSFET and medium-Vth MOSFET are provided by TSMC 0.18um CMOS process. but I never use them, all circuits I have designed apply standard-vth MOSFET.
So I am very interested where low-Vth MOSFET and medium-Vth MOSFET are useful.

Ziqi
 

E.g. for MOS diodes in tail current sources, in order not to loose too much Vds .
 
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in places where the resistive drop across the MOS must be insignificant you go for low threshold
 
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E.g. for MOS diodes in tail current sources, in order not to loose too much Vds .

in places where the resistive drop across the MOS must be insignificant you go for low threshold

I agree with you, both Erikl and Jeffrey. Although low-Vth MOSFET benefits low voltage drop, this technique is rarely introduced in textbooks or papers. So I suspect there are some drawbacks comparing with standard-Vth MOSFET. could you give me a sense?
 

each and every device has its own ups and downs based on the need served they are utilised by the public be it high low or standard ones

books mostly use more prevalent form of any device as they are easier to understand and practically testing them in amateur state is easier and simpler

low Vth devices the variations are very sensitive to voltage ip at mV levels that makes it not more popular for usage in labs and books for teaching newbies
 
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If Vth is low then Vth mismatches will cause more drain current error.
 
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... So I suspect there are some drawbacks comparing with standard-Vth MOSFET. could you give me a sense?

Low-Vth MOSFETs in "off" mode actually are still in weak inversion aka subthreshold mode, which means they have substantial leakage currents, considerably higher than standard-Vth MOSFETs.

So in order to disable circuits for very low stand-by current consumption, they should only be used in series with standard-Vth MOSFETs, which can be disabled to small leakage currents. Hence low-Vth MOSFETs usually aren't left alone between GND & VDD, but as auxiliary devices for current sourcing/sinking with low Vds losses.

If used as NMOS tail-current source for a degenerated differential NMOS stage, this has the advantage that only a low back-gate Vgb for the differential NMOS stage exists, so allowing for larger gm of this stage.
 
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