read 4-bit data from a line using textio

i make a code to read 4-bit image data from a line to form a matrix.
i have to read 16 4-bit data from a line to put in input.
i am attaching my code .
anyone plz. help me.




library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity image3 is
generic(m:integer:=4);
port(clk,rst,rd: in std_logic;
data_in: in std_logic_vector(3 downto 0) );
end image3;
architecture behaveral of image3 is
type memory is array (0 to m-1) of std_logic_vector (m-1 downto 0);
type memory_type is array (0 to m-1) of memory;
signal internal: memory_type;
signal rcntr,wcntr: std_logic_vector(1 downto 0);


begin
process(clk,rst)
variable row_inc,column_inc: integer range 0 to m:=0;
begin
if(rst='1') then
for row in 0 to 3 loop
for column in 0 to 3 loop
internal(row)(column)<=(others=>'0');
end loop;
end loop;

row_inc:=0;
column_inc:=0;
rcntr<=(others=>'0');
wcntr<=(others=>'0');

elsif (clk'event and clk='1') then
if rd='1' then
internal(row_inc)(column_inc)<= data_in;
column_inc:=column_inc+1;
if (column_inc=m) then
column_inc:=0;
row_inc:=row_inc+1;
if (row_inc=m) then
end if;
end if;
end if;
end if;
end process;
end behaveral;

------------------------------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity tb3 is
end tb3;
architecture tb3 of tb3 is
component image3 is
generic(m:integer:=4);
port(clk,rst,rd: in std_logic;
data_in : in std_logic_vector(3 downto 0));
end component image3;




type memory is array (0 to 3) of std_logic_vector (3 downto 0);
type memory_type is array (0 to 3) of memory;
signal clk1,rd1,rst1: std_logic;
signal data_in1: std_logic_vector(3 downto 0);
signal internal : memory_type;
--signal mid:std_logic_vector(63 downto 0);
begin
x: image3 port map(clk1,rst1,rd1,data_in1);

process
file infile: text open read_mode is "infile4";
file outfile: text open write_mode is "outfile1";
variable i,clk2,rd2,rst2: std_logic;
variable data_in2: std_logic_vector(3 downto 0);
variable data_in3: string;
variable internal1 : memory_type;
variable buf: line;
variable row_inc,column_inc: integer range 0 to 4:=0;

begin
rst1<='0';
rd1<='1';
clk1<='1';
wait for 20 ns;
clk1<= not clk1;
wait for 20 ns;

while not endfile(infile) loop
wait for 1 ns;
readline(infile,buf);
read(buf,data_in3);

data_in1<=data_in2;
end case;
end loop;




end loop;
end process;
end tb3;

:-x