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passing data between two simulations on the fly

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tariq786

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Hi,

I am wondering have any one of you played with the idea of passing data between simulations on the fly. For example, i wan to run two simulations where one is RTL simulation and the other one is gate-level simulation. Is it possible that one could pass data from RTL simulation to gate-level simulation or vice versa? If so, using what constructs and how?

Thanks for your response.

Kind Regards,
 

People do this all the time. From a Verilog module or VHDL entity perspective, there's no difference in how you connect up the port of a gate-level or RTL model.
 
Hi Dave!

Thanks for your response.It would be great if you could explain "HOW" it is done in Verilog? From your reply, it seems i can create two instantiations (one for RTL design and one for gate-level design) in the testbench. Am i thinking right?

Please elaborate. After finishing this, i shall share the sourcecode for edaboard users to play with.

Kind Regards,
tariq786
 

Hi Dave!
Thanks for your reply. This is purely an academic exercise. The aim is to see if gate-level simulation can be parallelized using RTL simulation "ON THE FLY"

Lets say i have a gate-level design and i can split the design into two partitions. The two partitions are still connected else these were two independent designs. Please see Figure 1.

52_1342718784.jpg


I want to use RTL simulation to feed in the two partitions rather than partition1 feeding partition2. RTL acts as predictor for gate-level simulation on both partitions. See Figure 2.

38_1342718784.jpg



So the key idea is that instead of partition1 feeding partition2, i want to feed each partition with equivalent RTL data.

The thing i am after is how to setup this environment where simulation data from RTL simulation is consumed by gate-level partition simulation

Hope i answered your question. If not, please let me know.
 

Hi Dave!

You wrote

"People do this all the time."

I am curious to know how?

Looking forward to your response.
 

In your figure 1, many people will simulate M1 at the gate level and M2 at the RTL level because they need the performance/capacity. Sometimes there are hundreds of blocks, and simulating them all at the gate-level is too costly, so the pick the blocks then need to perform gate-level simulation and swap them for the RTL. That's what I was referring to.

It wasn't until I saw your figure 2 that I understood what you were asking in your original question. It really doesn't matter to the simulator that you have a gate-level and RTL model, it's just two different models that you want to dynamically switch. Anyone who builds fault tolerant redundant hardware does something like this in their design. It's just that one of your models happens to be gatel-level, the other is RTL.

You've still only explained what you want to do, not why you want to do it. People do not simulate RTL vs gate comparisons anymore, you are only checking the validity of your synthesis tool, and there are formal equivalence tools that can do a much better job than dynamic simulation.
 
I think i highlighted why i want to do it.

Its an academic exercise to see if gate-level simulation can be parallelized using RTL as predictor.

If you have any specific questions, please let me know.

Once again, thank you for enriching me and all of us here with your hands on knowledge.

Kind Regards,
 

Hi Dave!

You wrote "People do this all the time."

Could you explain how?


Thanks
Kind Regards,
tariq786
 

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