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Could Verilog modules used together with VHDL modules?

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walkon

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Could I use a Verilog module to drive a VHDL model?
Because I want to present real numbers, but it seems Verilog
even couldn't support the real array. So could I use a VHDL
to do the computation with real numbers driven by a Verilog module?

Thanks.
 

Several packages support mixed language entries like Altera Quartus, Xilinx ISE and Synplify Pro...ispLever doesn't...


Already discussed few times here...have you searched before posting your question? I guess not (o;


And tell me..why did you post the question in "Analog circuit design" ????
 

two questions:
1- what's ispLever?
2- can this mixed mode been synthesised?
tnx
 

two questions:
1- what's ispLever?
Click to expand...

Software tool from Lattice for their devices. Could have been answered via a quick google search!

2- can this mixed mode been synthesised?
Click to expand...

What do you think it means when I say above tools mentioned support mixed languages? They are "synthesizing" tools!!
 

hi, Thanks for u reply very much.
secondly, I just realized that I posted in the wrong board.
I try to find my post on Analog Circuit Design just now. hehe
I thought I posted there, but seems not.
I am sorry for the inconvience I brought.
 

And, by looking back to the previous discussion, I get the idea that it could work.

And the reason why I need to use VHDL is because I want to process some real numbers. And could the ports in Verilog be defined as the format of real arrays?
 

Yes you can use with cadence
 

You can use module port to output real no.s in verilog
for that you need to use $bitstoreal and $realtobits system functions!
Check with Cadence verilog users guid
 

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