shaiko
Advanced Member level 5
Some Verilog questions :
1. Is "wire" used only for combinatorial logic and "reg" only for synchronous ?
2. The "assign" keyword together with the = operator is used only for "wire" while the <= operator is used only for "reg". correct ?
1. Is "wire" used only for combinatorial logic and "reg" only for synchronous ?
2. The "assign" keyword together with the = operator is used only for "wire" while the <= operator is used only for "reg". correct ?