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[MOVED] Help in finding online sources to teach how to design a PMOS input two -stage opamp

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roki

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[MOVED] Help in finding online sources to teach how to design a PMOS input two -stage opamp

Hi everyone, as seen from the title, i need your help in finding an example in how to design a PMOS input two stage opamp.
The type that will guide us in transistor sizing.
I've not been successful in finding.The examples in NMOS input is plenty though.
Please help.

Thank you!!
 

Re: Help in finding online sources to teach how to design a PMOS input two -stage opa

PMOS input is essentially the same as NMOS input. All the rules and guidelines for sizing remain the same. A nuance is that PMOS has less transconductance, which makes it better for current mirrors and worse for differential pairs. That aside, the diffpair should be wide and short, while the mirrors are long and narrow, just like an NMOS-input amplifier.

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PMOS input is essentially the same as NMOS input. All the rules and guidelines for sizing remain the same. A nuance is that PMOS has less transconductance, which makes it better for current mirrors and worse for differential pairs. That aside, the diffpair should be wide and short, while the mirrors are long and narrow, just like an NMOS-input amplifier.
 

Re: Help in finding online sources to teach how to design a PMOS input two -stage opa

- - - Updated - - -

PMOS input is essentially the same as NMOS input. All the rules and guidelines for sizing remain the same. A nuance is that PMOS has less transconductance, which makes it better for current mirrors and worse for differential pairs. That aside, the diffpair should be wide and short, while the mirrors are long and narrow, just like an NMOS-input amplifier.

Hi Zeker,

Since i already have the all transistor sizing for a NMOS input opamp, how can i implement those values into the PMOS model type?
 

Re: Help in finding online sources to teach how to design a PMOS input two -stage opa

For starters, try using the exact same sizes. Later, you can go back and check how the sizes affect the matching, and adjust them appropriately, but for now just try using the same sizes.

Hope this helps.
 

Re: Help in finding online sources to teach how to design a PMOS input two -stage opa

Hi ZekeR,
I've tried using the same sizes.However, simulation results is wrong. The only part that is correct is operating point analysis for the biasing current sector. The operating point of the remaining transistors is incorrect. Is there an alternative?

Thanks
 

Re: Help in finding online sources to teach how to design a PMOS input two -stage opa

Chances are, it's not because the sizings are wrong; you've probably configured the circuit wrong. Perhaps you've connected the non-inverting input to its output?

It would be helpful if you posted your schematic.
 

Re: Help in finding online sources to teach how to design a PMOS input two -stage opa

This is the model schematic of my PMOS input.


And I've connected the output to the inverting terminal.Yet it is still incorrect. Btw,this amplifier will be implemented to a LDO.
 

The problem with your circuit is that, for your PMOS input pair, you have mistaken the Body terminal for the Gate terminal; you have connected the PMOS Gates to VDD, and connected the body connections to the inverting and non-inverting inputs. The circuit cannot work like this.

Try swapping the connections and see if it works. Hopefully this helps.
 
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    roki

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Thank you ZekeR!!!
It is working now. I had not realized that i have accidentally flip it horizontally for both transistor.

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When i first design my NMOS input opamp, i let my ICMR Vmin be 0.6V.Now that i have alter it to a PMOS type, my testbench results shows that the PMOS opamp circuit is able to function within 0.1 to 0.3V. What may have cause it to be like that?
 
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The input common mode must be at a level such that the MOSFETs at the input stage turn "on." If you have an NMOS input stage, then bringing the common mode below 0.6V (for this circuit) turns the MOSFETs off; so this is your minimum limit. However, the maximum workable ICMR is almost to VDD. Once you get too close to VDD though, the active load stops behaving properly, and this becomes your upper limit.

With a PMOS input stage, the ICMR range is now from nearly the negative rail (when the active load starts misbehaving) to about 0.6V (or so) from the positive rail. It actually won't be 0.6V; it'll be Vov (of the PMOS current source) + Vth (of the PMOS diffpair) + Vov (of the PMOS diffpair) below the positive rail.

Technically, the same was true for the NMOS input: 0.6V was the voltage Vov (of the NMOS current source) + Vth (of the NMOS diffpair) + Vov (of the NMOS diffpair).

If you want to increase the ICMR further, you can use folded cascoding, or combined PMOS and NMOS input stages like below:
img1A.jpg

Hope this helps.
 
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    roki

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Thanks ZekeR, indeed it does help.

I have another enquiry.In my hand calculations when i first did my NMOS input two stage opamp, i did set the Vmin to 0.6V.However, when i run simulation, at 0.3V[the lowest] to 0.59V, the waveform seems to still show correct result.But my bias transistor is in linear region.
Hmm.... so even if one particular transistor is in linear, can the circuit still able to work?

Nevertheless, my design of Vmin=0.6V is IMO is correct as that is the minimum voltage where all transistor is in saturation.
I've read that proper ICMR has to meet this requirement where all transistors are in saturation.Pardon me if i structure it unclearly.
 

For the NMOS-input op-amp, when you bring the input common-mode between 0.3V and 0.59V and the bias transistor goes into triode, there is still current flowing through both MOSFETs in the diffpair, the circuit still has gain, and you still have negative feedback. However, the bias current decreases (because you no longer have full voltage across the bias transistor), which affects transconductance, frequency response, and offset voltage; also, because the bias transistor's output impedance decreases drastically, the CMRR and PSRR plummet. So although the op-amp might still function at this point, it doesn't function well.

I'm guessing that 0.3V is the NMOS threshold voltage in your process. Below this point, current essentially stops to flow, and the circuit ceases to function.

Hope this helps.
 
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