problem regarding simulation of vhdl code

hi can you please guide me in the following vhdl code . my task is to get the time required for changing the change signal from 0 to 1 and hit signal 0 to 1 . i write my code ..during synthesization i got warning index value(s) doesn't match but still it is synthesized. but the problem is that in test bench waveform change signal is becoming 1 from the starting . According to me i want to find out delay for changing change signal with respect to reconf signal but it is becoming 1 with reconf signal i want some solution for this problem .. please help me .

first of all - wheres the clock?

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Secondly - It looks like you're a software guy. I suggest you delete all this code and draw the circuit you want on a peice of paper before writing any VHDL. VHDL is the description language, so if you dont know what circuit you want, how do you expect your code to work?

As said above, you have tried to write a computer program that can run step by step on a processor. vhdl is not a programming language. It is a descriptor language. You need to to think about a circuit and then describe it in vhdl. It might look ok as is on the simulator but it won't in a real electronic circuit.

TonyM said:

As said above, you have tried to write a computer program that can run step by step on a processor. vhdl is not a programming language. It is a descriptor language. You need to to think about a circuit and then describe it in vhdl. It might look ok as is on the simulator but it won't in a real electronic circuit.

Click to expand...

As you people are saying that this is like of software programming I have been working on vhdl since last one month so may be some faults can be there .
I tried to do some changes in my program . I searched on the net and made it with the help of states.Now it is again synthesizing and implement design is also correct . but when i went for test bench wave form it is still not helpful . can you guide me that synthesis report of this program can be useful for me to find out the delay for becoming change signal from 0 to 1 . And there is one doubt also if it cant make any electronics circuit of code then why implement design becomes correct.
This time please give me any solution which i can take .. here is my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use ieee.numeric_bit.all ;
entity om is
Port ( clk : in STD_LOGIC; p0 : in std_logic_vector( 2 downto 0 ) ; p1 : in std_logic_vector(2 downto 0 ) ;
reconf : in STD_LOGIC ;reset : in std_logic ; change : out std_logic ; hit : out std_logic ; address : in std_logic_vector(5 downto 0 ));
end om;

architecture Behavioral of om is

type cacheblkpointer is array ( 0 to 7 ) of std_logic_vector( 5 downto 0 ) ;
signal cb : cacheblkpointer ;
type cacheproc is array (0 to 7) of std_logic ;
signal p : cacheproc ;
type set is array( 0 to 3 , 0 to 1) of std_logic_vector( 5 downto 0 ) ;
signal s : set ;
signal discard : std_logic_vector( 5 downto 0 ) ;
type state_type is (s0,s1,s2,s3, s4,s5); --type of state machine.
signal next_s: state_type; --current and next state declaration.
signal pu : integer ;

begin
process( reset , reconf , next_s)
variable f : std_logic_vector( 5 downto 0 );
variable n : integer ;
variable g : std_logic ;
variable l : integer ;
variable h : integer ;
variable k : integer ;
variable c1 : integer ;
variable c2 : integer ;
variable r : std_logic_vector(4 downto 0 ) ;
variable rd : integer ;
variable red : integer ;


begin
if(rising_edge(clk)) then
next_s <= s0 ;
case next_s is
when s0 =>
if ( reset = '1') then
cb(0) <= "010000" ;
cb(1) <= "010001" ;
cb(2) <= "010011" ;
cb(3) <= "010101" ;
cb(4) <= "011001" ;
cb(5) <= "010101" ;
cb(6) <= "010101" ;
cb(7) <= "010101" ;
p <= "01000101" ;
hit <= '0' ;
change <= '0' ;
n := 0 ;
end if ;

next_s <= s1 ;
when s1 =>
if( n < 8 ) then
f:= cb;

g := p ;
if( g = '0') then
pu <= conv_integer(unsigned(p0)) ;
else
pu <= conv_integer(unsigned(p1)) ;
end if ;
l := conv_integer(unsigned(f)) ;
for i in 1 to 63 loop
h := i-1 ;
k := i ;
c1 := pu * h ;
c2 := pu * k ;
if( c2 = l) then
r := "00000" ;
exit ;
end if ;
if( c2 > l) then
red := l - c1 ;
r := conv_std_logic_vector(red,5) ;
exit ;
end if ;
end loop ;
elsif ( n = 8) then
next_s <= s4 ;
end if ;
next_s <= s2;
when s2 =>
if (g = '0') then
rd := conv_integer(unsigned(r)) ;
else
rd := conv_integer(unsigned(r)) + pu ;
end if ;
next_s <= s3;
when s3 =>
if( rd > 0 and rd < 4) then
if(s(rd,0) = "000000") then
s(rd,0) <= "010000" ;
else
if(s(rd,1) = "000000") then
s(rd,1) <= "010000" ;
else
discard <= "010000" ;
end if ;
end if ;
else
discard <= "010000" ;
end if ;

n := n + 1 ;
next_s <= s1;
when s4 =>
change <= '1' ;
next_s <= s5 ;
when s5 =>
for i in 0 to 3 loop
for j in 0 to 1 loop
if(s(i,j) = address) then
hit <= '1' ;
else
hit <= '0' ;
end if ;
end loop ;
end loop ;
end case ;
end if ;
end process ;

end Behavioral;

it looks like all you did was wrap a clock around your code.
Did you draw the circuit on a peice of paper before you re-wrote the code?

Also - VHDL point - you cannot use std_logic_arith and numeric_std in the same file because they conflict. You should delete std_logic_arith because it is non-standard.

TrickyDicky said:

it looks like all you did was wrap a clock around your code.
Did you draw the circuit on a peice of paper before you re-wrote the code?

Also - VHDL point - you cannot use std_logic_arith and numeric_std in the same file because they conflict. You should delete std_logic_arith because it is non-standard.

Click to expand...

Actually it is a code for cache reconfiguration according to partition size so i jst read paper i dont know what is its circuit i just imagine that this can work like this , so i think there is no hope now for this thing..

thanks

I see some problems:
- The purpose of the design, e.g meaning of input signals isn't said. How can we suggest a solution?
- The second attempt shows considerable changes, e.g. implementation of a state machine. But it seems to be hastily designed, not all states can be reached.
- There's a dubious reset construct. Reset, either synchronous or asynchronous, should work unconditionally, not only in one state.
- Some code details raise doubts, if you understand the nature of signal assignments in a process at all.

Now it is again synthesizing and implement design is also correct.

Click to expand...

What do you mean with "correct" design? Hardware is behaving as intended? If so, you are talking about a simulation problem only?

The present VHDL code will in fact bring up some specific simulation problems due to uninitialized signals, e.g. next_s. Other than in real hardware, this signal will never get a defined state during simulation, all output signals will most likely stay undefined as well.

And there is one doubt also if it cant make any electronics circuit of code then why implement design becomes correct.

Click to expand...

A HDL design finally synthesis to a logic circuit, in so far any synthesizable HDL code can be represented by a circuit. VHDL offers different levels of abstraction, you can code a problem without directly referring to hardware structures. But there's a certain risk to end up in a non-synthesizable construct if you don't well understand the requirements of the underlying logic hardware.