shikha khandelwal
Newbie level 3
hi can you please guide me in the following vhdl code . my task is to get the time required for changing the change signal from 0 to 1 and hit signal 0 to 1 . i write my code ..during synthesization i got warning index value(s) doesn't match but still it is synthesized. but the problem is that in test bench waveform change signal is becoming 1 from the starting . According to me i want to find out delay for changing change signal with respect to reconf signal but it is becoming 1 with reconf signal i want some solution for this problem .. please help me .
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use ieee.numeric_std.all ; use ieee.std_logic_unsigned.all; use ieee.numeric_bit.all ; entity mi is port ( p0 : in std_logic_vector(2 downto 0 ) ; p1 : in std_logic_vector ( 2 downto 0 ) ; clk : in std_logic ; address : in unsigned(5 downto 0 ) ; reconf : in std_logic ; change : out std_logic ; hit : out std_logic) ; end mi; architecture Behavioral of mi is type entry is record addres : unsigned( 5 downto 0 ) ; proc : std_logic ; end record ; type cacheblkpointer is array ( 7 downto 0 ) of entry ; signal cb : cacheblkpointer ; type set is array( 0 to 3 , 0 to 1) of unsigned( 5 downto 0 ) ; signal s : set ; begin process(p0 , p1 , address , clk ) variable di : integer ; variable discard : unsigned( 5 downto 0 ) ; variable d : integer := 1; variable r : natural ; variable pr : std_logic ; variable x : positive ; variable re : integer ; variable m : unsigned(5 downto 0 ) ; begin cb(0).addres <= "010000" ; cb(1).addres <= "010100" ; cb(2).addres <= "010011" ; cb(3).addres <= "010011" ; cb(4).addres <= "011110" ; cb(5).addres <= "011110" ; cb(6).addres <= "010001" ; cb(7).addres <= "010111" ; cb(0).proc <= '0' ; cb(1).proc <= '1' ; cb(2).proc <= '0' ; cb(3).proc <= '0' ; cb(4).proc <= '1' ; cb(5).proc <= '0' ; cb(6).proc <= '1' ; cb(7).proc <= '0' ; s(0,0) <= "000000" ; s(0,1) <= "000000" ; s(1,0) <= "000000" ; s(1,1) <= "000000" ; s(2,0) <= "000000" ; s(2,1) <= "000000" ; s(3,0) <= "000000" ; s(3,1) <= "000000" ; change <= '0' ; hit <= '0' ; if(reconf = '1' ) then for n in 0 to 7 loop pr := cb(n).proc ; x := conv_integer (unsigned(cb(n).addres)) ; -- x = dividend if( pr = '0' ) then di := conv_integer (p0) ; d := conv_integer (p0) ; -- d = divider else d := conv_integer (p1) ; end if ; if( d = 1 ) then re := 0 ; --re stands for remainder . end if ; if( d > 1) then while ( d <= x) loop d := 2 * d ; end loop ; d := d / 2 ; x := x - d ; if( di < x) then d := di ; while( d <= x ) loop d := 2 * d ; end loop ; d := d /2 ; x := x - d ; end if ; if ( di = x) then r := 0 ; elsif (di > x) then r := conv_integer (p0) ; end if ; if(pr = '0') then re := r ; else re := r + conv_integer (p0) ; end if ; end if ; m := "000000" ; if( s(re,0) = m ) then s(re,0) <= cb(n).addres ; end if ; if (s(re,0) /= m) then if(s(re,1) = m) then s(re,1) <= cb(n).addres ; else discard := cb(n).addres ; end if ; end if ; end loop ; change <= '1' ; for i in 0 to 3 loop for j in 0 to 1 loop if ( s(i,j) = address) then hit <= '1' ; exit ; else hit <= '0' ; end if ; end loop ; end loop ; end if ; end process ; end Behavioral;
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