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Problem with en signal of speed clockand enable signal with slow clock

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omar-malek

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Hi to all,

i develop a system using VHDL language.
so i have to module one work with speed clock and generate signal enable for one cycle speed clock, this signal wired to other enable signal
that work with slow clock, so the problem the enable signal of second system (work with slow clock) haven't the sufficient time to activate a process with slow clock you can see the picture for more detail.

so any one give me an idea for this problem.

thank you in advance.
problem.PNG
 

We need more details on inputs and outputs, rates, jitter, latency or anything that can make it fail. (specs to avoid Murphy's Law)

Generally you need to provide 2 signal handshaking for a slower system to respond, like RTS/CTS.
If it is a synchronous system, then we need more details. But you may need a latch. Set = trigger Busy only if not busy then Reset when trigger is accepted and ready for next state.. In logic design, we prefer to use State diagrams and timing diagrams to show the requirements of the interface. See Finite State Machines (FSM or Mealey Moore design) Can you define the interface better in terms of function, so details can be realized.
 

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