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Do I need to build separate power ring for IO and the core?

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mvvijay78

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Power ring

Hi,
I would like to know if it needed to build a separarte power ring for IO and the core.Also how is the width of this ring determined,is it based on IR drop analysis.If IR drop tool is not availablke can these calculations be done manually.
Vicky
 

Power ring

If possible, dual power rings scheme as you described is preferred for noise isolation between IO and core. IR drop is one reason to decide the ring width. Another important reason is electro-migration issue. For example, if Metal3 can guarantee 1mA/um reliability, and your core consumes 20mA DC current, then 20um is the min requirement. Considering transient response, at least 3 times of 20um should be used. If the power ring is composed of multiple metal layers. The total width should be 60um.
 

Power ring

If possible, dual power rings scheme as you described is preferred for noise isolation between IO and core. IR drop is one reason to decide the ring width. Another important reason is electro-migration issue. For example, if Metal3 can guarantee 1mA/um reliability, and your core consumes 20mA average DC current, then 20um is the min requirement. Considering transient response, at least 3 times of 20um should be used. If the power ring is composed of multiple metal layers. The total width should be 60um.
 

Re: Power ring

Hi Vicky,

There are three methods for calculating the PG ring. They are
1) Electromigration
2) IR Drop
3) Peak Voltage

Usually, Electromigration and IR Drop is used for calculating the PG ring width and PG straps width. Which ever is the higher, that is used in the layout. This is for the core.

For the IO ring, if you add IO filler cells, IO rings gets completed. This is incase of Digital Designs.

-Sudhir
 

Re: Power ring

Hi sudhirtj,

Could u explain a bit more on peak voltage?
 

Re: Power ring

Hi Lokeyh,

The core PG width is calculated when the core consumes Peak current. The IR Drop calculation is done for the average current consumption of the core. Usually, this peak voltage drop calculation is not done for the calculation of PG width and i am not sure about the reason.
-Sudhir
 

Re: Power ring

All these things you mentioned about is current density considiration. But in my opinion the main purpose of the I/O guard ringis to prevent latch up of these I\O. Because during latch up test you pull or push large current into input or output. So any source or drain connected to I\O pin should be isolated from the rest of schematic by guard ring. Also PMOS and NMOS transistor of I\O connected to VDD and GND should be also isolated from each other by guard rings.
 

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