Eman kamel
Junior Member level 2
i am choosing design parameter for 45 nm technology NMOS transistor that is a part of interconnect buffer
in ptm model
http://ptm.asu.edu/cgi-bin/test/nanocmos.cgi
the suggested values for transistor width is 17.5 nm
for NangateOpenCellLibrary
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
the suggested chanel width is 50 nm
which value shall i pick?
thanks in advance
Eman
in ptm model
http://ptm.asu.edu/cgi-bin/test/nanocmos.cgi
the suggested values for transistor width is 17.5 nm
for NangateOpenCellLibrary
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
the suggested chanel width is 50 nm
which value shall i pick?
thanks in advance
Eman