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design of clock and data recovery circuit for the data at 2.4 Gbits/s at 130nm

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radioelektra

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I have to design a clock and data recovery circuit at 2.4 Gbits/s in 130nm process
...plz suggest how to start the design....thanks in advance...:|
 

Start by looking at CDR (Clock and Data Recovery) circuits like the Alexander or Hogge-Shin.
 

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