Error in cdesigner: internal timestep too small in transient analysis

Hii,
I'm getting the following error in cdesigner

**error** internal timestep too small in transient analysis

time = 0.61325E-06; delta = 0.25943E-14; numnit = 2658[/SIZE]


I tried all the combinations in transient analysis and I tried it with increasing the stepsize also. But its of no use. Actually the thing is, I'm getting this kind of error only when I do any modifications in my netlist and even though I again keep the same value I'm not able to remove that error. This is my netlist.final file


* HSPICE Netlist

.options POST=1 parhier=local

* Models section
* Include parameters
*.include 'my_model_parameters.inc'

* Include models
*.lib 'mymodel.lib' typ
.lib '/home/11011J6005/Desktop/amsd1/SAED_PDK90nm/hspice/SAED90nm.lib' TT_12


* Design variables section
* Define parameters
.param vdd = 1.8


* Structural netlist section
*Custom Designer (TM) Version E-2010.09
*Wed May 9 18:09:10 2012

.GLOBAL gnd! vdd!
********************************************************************************
* Library : sem2_prj
* Cell : inverter
* View : schematic
* View Search List : hspice hspiceD cmos.sch cmos_sch schematic
* View Stop List : hspice hspiceD
********************************************************************************
.subckt inverter net12 net13 vt_bulk_n_gnd! vt_bulk_p_vdd!
m0 net13 net12 net34 vt_bulk_n_gnd! n12 w=4u l=1u nf=1 m=1
m1 net13 net12 net19 vt_bulk_p_vdd! p12 w=21u l=1u nf=1 m=1
v9 gnd! net34 dc=1.8
v4 net19 gnd! dc=1.8
.ends inverter

********************************************************************************
* Library : sem2_prj
* Cell : transmision_gate
* View : schematic
* View Search List : hspice hspiceD cmos.sch cmos_sch schematic
* View Stop List : hspice hspiceD
********************************************************************************
.subckt transmision_gate net44 net45 net49 vt_bulk_p_vdd! vt_bulk_n_gnd!
m0 net45 net49 net44 vt_bulk_p_vdd! p12 w=15.0u l=3.0u nf=1 m=1
m1 net44 net67 net45 vt_bulk_n_gnd! n12 w=15.0u l=3.0u nf=1.0 m=1
xi2 net49 net67 vt_bulk_n_gnd! vt_bulk_p_vdd! inverter
.ends transmision_gate

********************************************************************************
* Library : sem2_prj
* Cell : Tn
* View : schematic
* View Search List : hspice hspiceD cmos.sch cmos_sch schematic
* View Stop List : hspice hspiceD
********************************************************************************
.subckt tn net4 net5 net6 vt_bulk_p_vdd! vt_bulk_n_gnd!
m0 net4 net6 net5 vt_bulk_p_vdd! p12 w=15.0u l=3.0u nf=1 m=1
m1 net5 net14 net4 vt_bulk_n_gnd! n12 w=15.0u l=3.0u nf=1 m=1
xi2 net6 net14 vt_bulk_n_gnd! vt_bulk_p_vdd! inverter
.ends tn

********************************************************************************
* Library : sem2_prj
* Cell : buffer
* View : schematic
* View Search List : hspice hspiceD cmos.sch cmos_sch schematic
* View Stop List : hspice hspiceD
********************************************************************************
.subckt buffer net147 net275
i8 net274 net261 dc=50u
v26 gnd! net273 dc=1.8
v9 net274 gnd! dc=1.8
m19 net261 net261 net273 net273 n12 w=4.0u l=2.0u nf=1 m=1
m18 net254 net261 net273 net273 n12 w=4.0u l=2.0u nf=1 m=1
m17 net147 net261 net273 net273 n12 w=4.0u l=2.0u nf=1 m=1
m16 net266 net275 net254 net273 n12 w=15.0u l=3.0u nf=1 m=1
m15 net225 net147 net254 net273 n12 w=15.0u l=3.0u nf=1 m=1
m22 net147 net266 net274 net274 p12 w=9.9u l=3.0u nf=1.0 m=1
m21 net225 net225 net274 net274 p12 w=5.0u l=3.0u nf=1 m=1
m20 net266 net225 net274 net274 p12 w=5.0u l=3.0u nf=1 m=1
.ends buffer

********************************************************************************
* Library : sem2_prj
* Cell : prj
* View : schematic
* View Search List : hspice hspiceD cmos.sch cmos_sch schematic
* View Stop List : hspice hspiceD
********************************************************************************
r30 net1713 gnd! r=1k
r29 net1734 net1713 r=1k
r28 net1714 net1734 r=1k
r24 net1733 net1714 r=1k
r23 net1712 net1733 r=1k
r22 net1732 net1712 r=1k
r21 net1710 net1732 r=1k
r17 net1731 net1710 r=1k
r16 net1711 net1731 r=1k
r15 net1735 net1711 r=1k
r14 net1709 net1735 r=1k
r4 net1730 net1709 r=1k
r3 net1708 net1730 r=1k
r2 net1736 net1708 r=1k
r1 net1715 net1736 r=1k
r0 net1197 net1715 r=1k
xi39 buf_ip net1748 b0 vdd! gnd! transmision_gate
xi31 net1744 net1713 b3 vdd! gnd! transmision_gate
xi30 net1746 net1743 b2 vdd! gnd! transmision_gate
xi28 net1743 net1714 b3 vdd! gnd! transmision_gate
xi24 net1738 net1712 b3 vdd! gnd! transmision_gate
xi23 net1737 net1739 b2 vdd! gnd! transmision_gate
xi21 net1739 net1710 b3 vdd! gnd! transmision_gate
xi20 net1749 net1737 b1 vdd! gnd! transmision_gate
xi17 net1742 net1711 b3 vdd! gnd! transmision_gate
xi16 net1745 net1741 b2 vdd! gnd! transmision_gate
xi14 net1741 net1709 b3 vdd! gnd! transmision_gate
xi9 net1740 net1708 b3 vdd! gnd! transmision_gate
xi8 net1747 net1750 b2 vdd! gnd! transmision_gate
xi6 net1750 net1715 b3 vdd! gnd! transmision_gate
xi11 net1748 net1747 b1 vdd! gnd! transmision_gate
v43 net1197 gnd! dc=1
v76 b1 gnd! dc=0 pulse ( 0 1.8 0 0 0 1m 2m )
v77 b0 gnd! dc=0 pulse ( 0 1.8 0 0 0 0.5m 1m )
v60 b2 gnd! dc=0 pulse ( 0 1.8 0 0 0 2m 4m )
v57 b3 gnd! dc=0 pulse ( 0 1.8 0 0 0 4m 8m )
xi61 b2 net1747 net1740 vdd! gnd! tn
xi64 b2 net1746 net1744 vdd! gnd! tn
xi68 b3 net1739 net1732 vdd! gnd! tn
xi69 b3 net1742 net1731 vdd! gnd! tn
xi62 b2 net1745 net1742 vdd! gnd! tn
xi65 b3 net1744 gnd! vdd! gnd! tn
xi70 b3 net1741 net1735 vdd! gnd! tn
xi71 b3 net1740 net1730 vdd! gnd! tn
xi66 b3 net1743 net1734 vdd! gnd! tn
xi72 b3 net1750 net1736 vdd! gnd! tn
xi73 b0 buf_ip net1749 vdd! gnd! tn
xi63 b2 net1737 net1738 vdd! gnd! tn
xi67 b3 net1738 net1733 vdd! gnd! tn
xi74 b1 net1749 net1746 vdd! gnd! tn
xi75 b1 net1748 net1745 vdd! gnd! tn
xi84 out buf_ip buffer



* Analysis section
* Transient Analyses
.tran 1u 100m START=0


* AC Analyses
*.AC DEC 50 1 100Meg

.end




Please let me know if i'm not clear.

Re: Error in cdesigner..

Your problem is most likely a floating node. It is not easy to see without a schematic. As you seem to have several transmission gates, that could be the problem. Try adding some very high value resistors from various nodes to ground around the transmission gates and see if that helps. 1G ohm should do.

Keith

---------- Post added at 05:57 ---------- Previous post was at 05:51 ----------

Actually, one other thing to try - a lot shorter simulation. You are running for 100ms which is very long. Try 10us first and use faster stimulus pulses.

One other strange thing is you have 1.8V power supply voltage sources within a subcircuit.

Re: Error in cdesigner..

keith1200rs said:

Your problem is most likely a floating node. It is not easy to see without a schematic. As you seem to have several transmission gates, that could be the problem. Try adding some very high value resistors from various nodes to ground around the transmission gates and see if that helps. 1G ohm should do.

Keith

---------- Post added at 05:57 ---------- Previous post was at 05:51 ----------

Actually, one other thing to try - a lot shorter simulation. You are running for 100ms which is very long. Try 10us first and use faster stimulus pulses.

One other strange thing is you have 1.8V power supply voltage sources within a subcircuit.

Click to expand...

I checked it, there are no floating nodes....

Re: Error in cdesigner..

Without a schematic it is impossible to tell. A floating node is one where no DC path exists to ground. It will not necessarily look like a dangling node. It could be the junction of two MOSFET drains where both are turned off.

Keith.