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Problem with current sink transistor melting in OpAmp design

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OP AMP design IDEA

i have designed a three stage op amp using level one spice model using generci libraies in cadence of L=1.6 micro. I designed everythign as per equations and got everything done but while simulating the current sink transistor is melting during simulation.

MAx current i took while designing is 5mA because of restrictions in generic and low value of Kp, Kn and channel length modulation factors. but after simlulation and observing the branch currents. th ecurretn in sink is apprx more than what it can handle .

Can any one please help
 

Re: OP AMP design IDEA

Why three stages when two stage can do the job?
 

Re: OP AMP design IDEA

1. 3 stages can make ur system unstable.
2. Post ur schematic for better understanding of problem
 

OP AMP design IDEA

How much is the simulated branch current? Please post the schematic, at least the schematic related to the problematic current sink.
 

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