sages
Newbie level 6
Hi guys,
I'm confused about set_input_delay in DC. Does it mean the delay from the signal source through the I/O pad to the input port (no matter the port is register's or gate's) ? Or it means the delay from the signal source through the I/O pad to the first stage's register in the design?
Another question is : if I have two different designed modules A and B, and one output of A is connected to one input of B. What if both output of A and input of B are registered, should the set_input_delay be zero????
I'm confused about set_input_delay in DC. Does it mean the delay from the signal source through the I/O pad to the input port (no matter the port is register's or gate's) ? Or it means the delay from the signal source through the I/O pad to the first stage's register in the design?
Another question is : if I have two different designed modules A and B, and one output of A is connected to one input of B. What if both output of A and input of B are registered, should the set_input_delay be zero????